| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 119 case ISD::Constant: in getOperationName()
148 case ISD::INTRINSIC_WO_CHAIN: in getOperationName()
149 case ISD::INTRINSIC_VOID: in getOperationName()
150 case ISD::INTRINSIC_W_CHAIN: { in getOperationName()
163 case ISD::TargetConstant: in getOperationName()
426 case ISD::PSEUDO_PROBE: in getOperationName()
432 case ISD::PREALLOCATED_SETUP: in getOperationName()
434 case ISD::PREALLOCATED_ARG: in getOperationName()
464 case ISD::CONDCODE: in getOperationName()
512 case ISD::STACKMAP: in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 340 case ISD::ADD: in LegalizeOp()
341 case ISD::SUB: in LegalizeOp()
342 case ISD::MUL: in LegalizeOp()
356 case ISD::AND: in LegalizeOp()
357 case ISD::OR: in LegalizeOp()
358 case ISD::XOR: in LegalizeOp()
359 case ISD::SHL: in LegalizeOp()
360 case ISD::SRA: in LegalizeOp()
361 case ISD::SRL: in LegalizeOp()
366 case ISD::ABS: in LegalizeOp()
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| H A D | LegalizeDAG.cpp | 761 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
1739 ISD::ADD : ISD::SUB; in ExpandDYNAMIC_STACKALLOC()
2307 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3552 case ISD::SMAX: Pred = ISD::SETGT; break; in ExpandNode()
3553 case ISD::SMIN: Pred = ISD::SETLT; break; in ExpandNode()
3554 case ISD::UMAX: Pred = ISD::SETUGT; break; in ExpandNode()
3555 case ISD::UMIN: Pred = ISD::SETULT; break; in ExpandNode()
3717 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI; in ExpandNode()
3732 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; in ExpandNode()
3860 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB; in ExpandNode()
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| H A D | LegalizeIntegerTypes.cpp | 1012 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSHLSAT()
1191 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_SADDSUBO()
1574 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_UADDSUBO()
2957 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; in ExpandShiftWithKnownAmountBit()
2959 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; in ExpandShiftWithKnownAmountBit()
3207 N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY, in ExpandIntRes_ADDSUB()
3484 N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY; in ExpandIntRes_SADDSUBO_CARRY()
3962 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT, in ExpandIntRes_LOAD()
4462 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in ExpandIntRes_ShiftThroughStack()
5021 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
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| H A D | LegalizeVectorTypes.cpp | 1135 case ISD::ADD: case ISD::VP_ADD: in SplitVectorResult()
1136 case ISD::SUB: case ISD::VP_SUB: in SplitVectorResult()
1137 case ISD::MUL: case ISD::VP_MUL: in SplitVectorResult()
1153 case ISD::AND: case ISD::VP_AND: in SplitVectorResult()
1154 case ISD::OR: case ISD::VP_OR: in SplitVectorResult()
1155 case ISD::XOR: case ISD::VP_XOR: in SplitVectorResult()
1156 case ISD::SHL: case ISD::VP_SHL: in SplitVectorResult()
1157 case ISD::SRA: case ISD::VP_ASHR: in SplitVectorResult()
1158 case ISD::SRL: case ISD::VP_LSHR: in SplitVectorResult()
1177 case ISD::FMA: case ISD::VP_FMA: in SplitVectorResult()
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| H A D | TargetLowering.cpp | 2219 (Opc == ISD::SMIN || Opc == ISD::UMAX) ? ISD::OR : ISD::AND; in SimplifyDemandedBits()
4255 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
4283 ISD::CondCode CmpCond = Cond == ISD::SETEQ ? ISD::SETUGT : ISD::SETULE; in simplifySetCCWithCTPOP()
4865 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
4885 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
8262 ISD::CondCode Pred = Opcode == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; in createSelectForFMINNUM_FMAXNUM()
9985 return buildMinMax(ISD::SETGT, ISD::SETGE, ISD::SETLT, ISD::SETLE); in expandIntMINMAX()
9987 return buildMinMax(ISD::SETLT, ISD::SETLE, ISD::SETGT, ISD::SETGE); in expandIntMINMAX()
9989 return buildMinMax(ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE); in expandIntMINMAX()
9991 return buildMinMax(ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE); in expandIntMINMAX()
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| H A D | LegalizeFloatTypes.cpp | 115 case ISD::FPOWI: in SoftenFloatResult()
116 case ISD::FLDEXP: in SoftenFloatResult()
118 case ISD::FFREXP: in SoftenFloatResult()
2809 case ISD::FABS: in SoftPromoteHalfResult()
2812 case ISD::FCOS: in SoftPromoteHalfResult()
2813 case ISD::FEXP: in SoftPromoteHalfResult()
2817 case ISD::FLOG: in SoftPromoteHalfResult()
2821 case ISD::FNEG: in SoftPromoteHalfResult()
2826 case ISD::FSIN: in SoftPromoteHalfResult()
2832 case ISD::FADD: in SoftPromoteHalfResult()
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| H A D | DAGCombiner.cpp | 1523 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD in PromoteOperand()
1760 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD in PromoteLoad()
4173 if (SDValue R = MatchSubMaxMin(ISD::SMAX, ISD::SMIN, ISD::ABDS)) in visitSUB()
4175 if (SDValue R = MatchSubMaxMin(ISD::UMAX, ISD::UMIN, ISD::ABDU)) in visitSUB()
5535 return CC == ISD::SETLT ? ISD::SMIN : (CC == ISD::SETGT ? ISD::SMAX : 0); in isSaturatingMinMax()
5570 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; in isSaturatingMinMax()
7492 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
7497 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) in isBSwapHWordElement()
14219 ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD; in reduceLoadWidth()
18486 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); in SplitIndexingFromLoad()
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| H A D | SelectionDAG.cpp | 561 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType()
564 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
576 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { in getSetCCSwappedOperands()
599 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, EVT Type) { in getSetCCInverse()
603 ISD::CondCode ISD::GlobalISel::getSetCCInverse(ISD::CondCode Op, in getSetCCInverse()
627 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
648 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
656 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
2528 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) in FoldSetCC()
6000 if (Opcode == ISD::AND || Opcode == ISD::MUL) in FoldValueWithUndef()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 316 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
338 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
340 if (ISD == ISD::UDIV) in getArithmeticInstrCost()
1027 ISD = ISD::MUL; in getArithmeticInstrCost()
1433 (ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || in getArithmeticInstrCost()
3041 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && in getCastInstrCost()
3058 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && in getCastInstrCost()
4045 ISD = ISD::ABS; in getIntrinsicInstrCost()
4054 ISD = ISD::CTLZ; in getIntrinsicInstrCost()
4170 ISD = ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_UNDEF : ISD::CTLZ_ZERO_UNDEF; in getIntrinsicInstrCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 343 setOperationAction({ISD::FCEIL, ISD::FPOW, ISD::FABS, ISD::FFLOOR, in AMDGPUTargetLowering()
344 ISD::FROUNDEVEN, ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM}, in AMDGPUTargetLowering()
351 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
367 setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, in AMDGPUTargetLowering()
412 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, VT, in AMDGPUTargetLowering()
424 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal); in AMDGPUTargetLowering()
438 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
442 setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i32, in AMDGPUTargetLowering()
446 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering()
480 ISD::FADD, ISD::FCEIL, ISD::FCOS, in AMDGPUTargetLowering()
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| H A D | R600ISelLowering.cpp | 50 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) in R600TargetLowering()
58 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
61 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
87 setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT, in R600TargetLowering()
88 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE, in R600TargetLowering()
89 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
92 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
104 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR}, in R600TargetLowering()
153 setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, MVT::i32, in R600TargetLowering()
188 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 84 namespace ISD {
1422 case ISD::LOAD:
1472 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||
1672 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1830 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1908 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
2554 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2698 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
3098 namespace ISD {
3188 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 850 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
860 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
865 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
878 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP}, VT, in initActions()
886 ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT}, in initActions()
899 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
900 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
935 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, in initActions()
936 ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT, in initActions()
937 ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, ISD::LROUND, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 602 if ((ISD == ISD::SIGN_EXTEND || ISD == ISD::ZERO_EXTEND) && in getCastInstrCost()
824 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
840 if (ISD == ISD::TRUNCATE && ST->hasMVEIntegerOps() && in getCastInstrCost()
925 if (CostKind == TTI::TCK_CodeSize && ISD == ISD::SELECT && in getCmpSelInstrCost()
1331 case ISD::AND: in getArithmeticInstrCost()
1332 case ISD::XOR: in getArithmeticInstrCost()
1334 case ISD::OR: in getArithmeticInstrCost()
1681 if ((ISD == ISD::FADD || ISD == ISD::FMUL) && in getArithmeticReductionCost()
1710 if ((ISD == ISD::AND || ISD == ISD::OR || ISD == ISD::XOR) && in getArithmeticReductionCost()
1763 switch (ISD) { in getExtendedReductionCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 343 case ISD::SRL: in LowerOperation()
978 case ISD::SHL: in LowerShifts()
983 case ISD::SRA: in LowerShifts()
984 case ISD::SRL: in LowerShifts()
1050 case ISD::SETEQ: in EmitCMP()
1057 case ISD::SETNE: in EmitCMP()
1064 case ISD::SETULE: in EmitCMP()
1092 case ISD::SETLE: in EmitCMP()
1095 case ISD::SETGE: in EmitCMP()
1106 case ISD::SETGT: in EmitCMP()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 279 setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL}, in RISCVTargetLowering()
429 ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in RISCVTargetLowering()
430 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, in RISCVTargetLowering()
431 ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO}; in RISCVTargetLowering()
434 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in RISCVTargetLowering()
438 ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FRINT, ISD::FROUND, in RISCVTargetLowering()
907 ISD::SETO, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in RISCVTargetLowering()
908 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUO, in RISCVTargetLowering()
909 ISD::SETGT, ISD::SETOGT, ISD::SETGE, ISD::SETOGE, in RISCVTargetLowering()
1177 setOperationAction({ISD::ADD, ISD::MUL, ISD::SUB, ISD::AND, ISD::OR, in RISCVTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 439 setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT}); in initializeHVXLowering()
1585 unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in resizeToWidth()
2075 assert(Opc == ISD::FSHL || Opc == ISD::FSHR); in LowerHvxFunnelShift()
2178 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
2451 unsigned ShRight = Signed ? ISD::SRA : ISD::SRL; in emitHvxShiftRightRnd()
2676 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT || in EqualizeFpIntConversion()
2677 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in EqualizeFpIntConversion()
2687 bool Signed = Opc == ISD::FP_TO_SINT || Opc == ISD::SINT_TO_FP; in EqualizeFpIntConversion()
2699 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT); in ExpandHvxFpToInt()
2828 assert(Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in ExpandHvxIntToFp()
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| H A D | HexagonISelLowering.cpp | 1540 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
1589 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1626 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV, in HexagonTargetLowering()
1627 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
1628 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI, in HexagonTargetLowering()
1630 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1631 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::BSWAP, ISD::BITREVERSE, in HexagonTargetLowering()
1633 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1634 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
1635 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.h | 73 case ISD::SETEQ: in intCondCode2Icc()
75 case ISD::SETNE: in intCondCode2Icc()
77 case ISD::SETLT: in intCondCode2Icc()
79 case ISD::SETGT: in intCondCode2Icc()
81 case ISD::SETLE: in intCondCode2Icc()
83 case ISD::SETGE: in intCondCode2Icc()
103 case ISD::SETEQ: in fpCondCode2Fcc()
106 case ISD::SETNE: in fpCondCode2Fcc()
109 case ISD::SETLT: in fpCondCode2Fcc()
112 case ISD::SETGT: in fpCondCode2Fcc()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1523 case ISD::SETEQ: in intCondCCodeToRcond()
1525 case ISD::SETNE: in intCondCCodeToRcond()
1527 case ISD::SETLT: in intCondCCodeToRcond()
1529 case ISD::SETGT: in intCondCCodeToRcond()
2930 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
3139 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3141 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3290 case ISD::FABS: in LowerOperation()
3294 case ISD::ADDC: in LowerOperation()
3295 case ISD::ADDE: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 76 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i8, Promote); in M68kTargetLowering()
77 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i16, Legal); in M68kTargetLowering()
79 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, Legal); in M68kTargetLowering()
81 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, LibCall); in M68kTargetLowering()
85 {ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
92 for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
97 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
103 for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) in M68kTargetLowering()
306 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 120 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
121 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
125 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
129 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
144 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, in WebAssemblyTargetLowering()
145 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, in WebAssemblyTargetLowering()
146 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
230 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) in WebAssemblyTargetLowering()
235 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in WebAssemblyTargetLowering()
250 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 698 ISD::BR_CC, ISD::FADD, ISD::FSUB, in AArch64TargetLowering()
699 ISD::FMUL, ISD::FDIV, ISD::FMA, in AArch64TargetLowering()
715 for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in AArch64TargetLowering()
987 setTargetDAGCombine({ISD::ADD, ISD::ABS, ISD::SUB, ISD::XOR, ISD::SINT_TO_FP, in AArch64TargetLowering()
1082 ISD::FMUL, ISD::FDIV, ISD::FMA, in AArch64TargetLowering()
1097 {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP, ISD::UINT_TO_FP, in AArch64TargetLowering()
1098 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
1241 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1242 ISD::FROUND, ISD::FROUNDEVEN, ISD::STRICT_FFLOOR, in AArch64TargetLowering()
1738 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 141 setTargetDAGCombine({ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR}); in LanaiTargetLowering()
176 case ISD::MUL: in LowerOperation()
178 case ISD::BR_CC: in LowerOperation()
190 case ISD::SETCC: in LowerOperation()
813 case ISD::SETEQ: in IntCondCCodeToICC()
861 case ISD::SETO: in IntCondCCodeToICC()
1476 case ISD::ADD: in PerformDAGCombine()
1477 case ISD::OR: in PerformDAGCombine()
1478 case ISD::XOR: in PerformDAGCombine()
1480 case ISD::AND: in PerformDAGCombine()
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