Lines Matching refs:ISD
579 case ISD::ATOMIC_CMP_SWAP: { in getOUTLINE_ATOMIC()
583 case ISD::ATOMIC_SWAP: { in getOUTLINE_ATOMIC()
587 case ISD::ATOMIC_LOAD_ADD: { in getOUTLINE_ATOMIC()
591 case ISD::ATOMIC_LOAD_OR: { in getOUTLINE_ATOMIC()
595 case ISD::ATOMIC_LOAD_CLR: { in getOUTLINE_ATOMIC()
599 case ISD::ATOMIC_LOAD_XOR: { in getOUTLINE_ATOMIC()
629 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) in getSYNC()
630 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) in getSYNC()
631 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) in getSYNC()
632 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) in getSYNC()
633 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) in getSYNC()
634 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) in getSYNC()
635 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) in getSYNC()
636 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) in getSYNC()
637 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) in getSYNC()
638 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) in getSYNC()
639 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) in getSYNC()
640 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) in getSYNC()
700 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { in InitCmpLibcallCCs()
701 std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID); in InitCmpLibcallCCs()
702 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
703 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
704 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
705 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
706 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
707 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
708 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
709 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
710 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs()
711 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs()
712 CCs[RTLIB::OGE_F128] = ISD::SETGE; in InitCmpLibcallCCs()
713 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; in InitCmpLibcallCCs()
714 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
715 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
716 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
717 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; in InitCmpLibcallCCs()
718 CCs[RTLIB::OLE_F32] = ISD::SETLE; in InitCmpLibcallCCs()
719 CCs[RTLIB::OLE_F64] = ISD::SETLE; in InitCmpLibcallCCs()
720 CCs[RTLIB::OLE_F128] = ISD::SETLE; in InitCmpLibcallCCs()
721 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; in InitCmpLibcallCCs()
722 CCs[RTLIB::OGT_F32] = ISD::SETGT; in InitCmpLibcallCCs()
723 CCs[RTLIB::OGT_F64] = ISD::SETGT; in InitCmpLibcallCCs()
724 CCs[RTLIB::OGT_F128] = ISD::SETGT; in InitCmpLibcallCCs()
725 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; in InitCmpLibcallCCs()
726 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
727 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
728 CCs[RTLIB::UO_F128] = ISD::SETNE; in InitCmpLibcallCCs()
729 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
785 for (ISD::NodeType NT : enum_seq(ISD::DELETED_NODE, ISD::BUILTIN_OP_END, in initActions()
793 setLoadExtAction(ISD::EXTLOAD, AVT, VT, Expand); in initActions()
794 setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand); in initActions()
797 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
798 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { in initActions()
810 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); in initActions()
811 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
818 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
819 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { in initActions()
827 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
830 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
831 ISD::FMINNUM, ISD::FMAXNUM, in initActions()
832 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, in initActions()
833 ISD::FMINIMUM, ISD::FMAXIMUM, in initActions()
834 ISD::FMAD, ISD::SMIN, in initActions()
835 ISD::SMAX, ISD::UMIN, in initActions()
836 ISD::UMAX, ISD::ABS, in initActions()
837 ISD::FSHL, ISD::FSHR, in initActions()
838 ISD::SADDSAT, ISD::UADDSAT, in initActions()
839 ISD::SSUBSAT, ISD::USUBSAT, in initActions()
840 ISD::SSHLSAT, ISD::USHLSAT, in initActions()
841 ISD::SMULFIX, ISD::SMULFIXSAT, in initActions()
842 ISD::UMULFIX, ISD::UMULFIXSAT, in initActions()
843 ISD::SDIVFIX, ISD::SDIVFIXSAT, in initActions()
844 ISD::UDIVFIX, ISD::UDIVFIXSAT, in initActions()
845 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
846 ISD::IS_FPCLASS}, in initActions()
850 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
851 ISD::SMULO, ISD::UMULO}, in initActions()
855 setOperationAction({ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY, in initActions()
856 ISD::SADDO_CARRY, ISD::SSUBO_CARRY}, in initActions()
860 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
865 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
869 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
872 setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, in initActions()
875 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand); in initActions()
878 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP}, VT, in initActions()
884 {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, ISD::ANY_EXTEND_VECTOR_INREG, in initActions()
885 ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG, in initActions()
886 ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT}, in initActions()
891 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); in initActions()
895 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); in initActions()
899 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
900 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
901 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
902 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, in initActions()
903 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM, in initActions()
904 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL}, in initActions()
908 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
912 setOperationAction(ISD::SDOPC, VT, Expand); in initActions()
916 setOperationAction(ISD::GET_FPENV, VT, Expand); in initActions()
917 setOperationAction(ISD::SET_FPENV, VT, Expand); in initActions()
918 setOperationAction(ISD::RESET_FPENV, VT, Expand); in initActions()
922 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); in initActions()
925 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); in initActions()
930 setOperationAction(ISD::ConstantFP, in initActions()
935 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, in initActions()
936 ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT, in initActions()
937 ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, ISD::LROUND, in initActions()
938 ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN}, in initActions()
942 setOperationAction(ISD::TRAP, MVT::Other, Expand); in initActions()
946 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); in initActions()
948 setOperationAction(ISD::UBSANTRAP, MVT::Other, Expand); in initActions()
950 setOperationAction(ISD::GET_FPENV_MEM, MVT::Other, Expand); in initActions()
951 setOperationAction(ISD::SET_FPENV_MEM, MVT::Other, Expand); in initActions()
954 setOperationAction(ISD::GET_FPMODE, VT, Expand); in initActions()
955 setOperationAction(ISD::SET_FPMODE, VT, Expand); in initActions()
957 setOperationAction(ISD::RESET_FPMODE, MVT::Other, Expand); in initActions()
986 case ISD::SDIV: in canOpTrap()
987 case ISD::UDIV: in canOpTrap()
988 case ISD::SREM: in canOpTrap()
989 case ISD::UREM: in canOpTrap()
1720 SmallVectorImpl<ISD::OutputArg> &Outs, in GetReturnInfo()
1729 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in GetReturnInfo()
1732 ExtendKind = ISD::SIGN_EXTEND; in GetReturnInfo()
1734 ExtendKind = ISD::ZERO_EXTEND; in GetReturnInfo()
1740 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
1752 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); in GetReturnInfo()
1763 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
1852 case FNeg: return ISD::FNEG; in InstructionOpcodeToISD()
1853 case Add: return ISD::ADD; in InstructionOpcodeToISD()
1854 case FAdd: return ISD::FADD; in InstructionOpcodeToISD()
1855 case Sub: return ISD::SUB; in InstructionOpcodeToISD()
1856 case FSub: return ISD::FSUB; in InstructionOpcodeToISD()
1857 case Mul: return ISD::MUL; in InstructionOpcodeToISD()
1858 case FMul: return ISD::FMUL; in InstructionOpcodeToISD()
1859 case UDiv: return ISD::UDIV; in InstructionOpcodeToISD()
1860 case SDiv: return ISD::SDIV; in InstructionOpcodeToISD()
1861 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
1862 case URem: return ISD::UREM; in InstructionOpcodeToISD()
1863 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
1864 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
1865 case Shl: return ISD::SHL; in InstructionOpcodeToISD()
1866 case LShr: return ISD::SRL; in InstructionOpcodeToISD()
1867 case AShr: return ISD::SRA; in InstructionOpcodeToISD()
1868 case And: return ISD::AND; in InstructionOpcodeToISD()
1869 case Or: return ISD::OR; in InstructionOpcodeToISD()
1870 case Xor: return ISD::XOR; in InstructionOpcodeToISD()
1872 case Load: return ISD::LOAD; in InstructionOpcodeToISD()
1873 case Store: return ISD::STORE; in InstructionOpcodeToISD()
1878 case Trunc: return ISD::TRUNCATE; in InstructionOpcodeToISD()
1879 case ZExt: return ISD::ZERO_EXTEND; in InstructionOpcodeToISD()
1880 case SExt: return ISD::SIGN_EXTEND; in InstructionOpcodeToISD()
1881 case FPToUI: return ISD::FP_TO_UINT; in InstructionOpcodeToISD()
1882 case FPToSI: return ISD::FP_TO_SINT; in InstructionOpcodeToISD()
1883 case UIToFP: return ISD::UINT_TO_FP; in InstructionOpcodeToISD()
1884 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()
1885 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
1886 case FPExt: return ISD::FP_EXTEND; in InstructionOpcodeToISD()
1887 case PtrToInt: return ISD::BITCAST; in InstructionOpcodeToISD()
1888 case IntToPtr: return ISD::BITCAST; in InstructionOpcodeToISD()
1889 case BitCast: return ISD::BITCAST; in InstructionOpcodeToISD()
1890 case AddrSpaceCast: return ISD::ADDRSPACECAST; in InstructionOpcodeToISD()
1891 case ICmp: return ISD::SETCC; in InstructionOpcodeToISD()
1892 case FCmp: return ISD::SETCC; in InstructionOpcodeToISD()
1895 case Select: return ISD::SELECT; in InstructionOpcodeToISD()
1899 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; in InstructionOpcodeToISD()
1900 case InsertElement: return ISD::INSERT_VECTOR_ELT; in InstructionOpcodeToISD()
1901 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
1902 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1903 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1905 case Freeze: return ISD::FREEZE; in InstructionOpcodeToISD()
2284 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote && in isLoadBitCastBeneficial()
2285 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()) in isLoadBitCastBeneficial()