Lines Matching refs:ISD
64 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
65 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
67 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
68 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
70 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
71 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
73 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
74 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
76 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
77 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
79 setOperationAction(ISD::LOAD, MVT::v6f32, Promote); in AMDGPUTargetLowering()
80 AddPromotedToType(ISD::LOAD, MVT::v6f32, MVT::v6i32); in AMDGPUTargetLowering()
82 setOperationAction(ISD::LOAD, MVT::v7f32, Promote); in AMDGPUTargetLowering()
83 AddPromotedToType(ISD::LOAD, MVT::v7f32, MVT::v7i32); in AMDGPUTargetLowering()
85 setOperationAction(ISD::LOAD, MVT::v8f32, Promote); in AMDGPUTargetLowering()
86 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
88 setOperationAction(ISD::LOAD, MVT::v9f32, Promote); in AMDGPUTargetLowering()
89 AddPromotedToType(ISD::LOAD, MVT::v9f32, MVT::v9i32); in AMDGPUTargetLowering()
91 setOperationAction(ISD::LOAD, MVT::v10f32, Promote); in AMDGPUTargetLowering()
92 AddPromotedToType(ISD::LOAD, MVT::v10f32, MVT::v10i32); in AMDGPUTargetLowering()
94 setOperationAction(ISD::LOAD, MVT::v11f32, Promote); in AMDGPUTargetLowering()
95 AddPromotedToType(ISD::LOAD, MVT::v11f32, MVT::v11i32); in AMDGPUTargetLowering()
97 setOperationAction(ISD::LOAD, MVT::v12f32, Promote); in AMDGPUTargetLowering()
98 AddPromotedToType(ISD::LOAD, MVT::v12f32, MVT::v12i32); in AMDGPUTargetLowering()
100 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); in AMDGPUTargetLowering()
101 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
103 setOperationAction(ISD::LOAD, MVT::v32f32, Promote); in AMDGPUTargetLowering()
104 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
106 setOperationAction(ISD::LOAD, MVT::i64, Promote); in AMDGPUTargetLowering()
107 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
109 setOperationAction(ISD::LOAD, MVT::v2i64, Promote); in AMDGPUTargetLowering()
110 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32); in AMDGPUTargetLowering()
112 setOperationAction(ISD::LOAD, MVT::f64, Promote); in AMDGPUTargetLowering()
113 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32); in AMDGPUTargetLowering()
115 setOperationAction(ISD::LOAD, MVT::v2f64, Promote); in AMDGPUTargetLowering()
116 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32); in AMDGPUTargetLowering()
118 setOperationAction(ISD::LOAD, MVT::v3i64, Promote); in AMDGPUTargetLowering()
119 AddPromotedToType(ISD::LOAD, MVT::v3i64, MVT::v6i32); in AMDGPUTargetLowering()
121 setOperationAction(ISD::LOAD, MVT::v4i64, Promote); in AMDGPUTargetLowering()
122 AddPromotedToType(ISD::LOAD, MVT::v4i64, MVT::v8i32); in AMDGPUTargetLowering()
124 setOperationAction(ISD::LOAD, MVT::v3f64, Promote); in AMDGPUTargetLowering()
125 AddPromotedToType(ISD::LOAD, MVT::v3f64, MVT::v6i32); in AMDGPUTargetLowering()
127 setOperationAction(ISD::LOAD, MVT::v4f64, Promote); in AMDGPUTargetLowering()
128 AddPromotedToType(ISD::LOAD, MVT::v4f64, MVT::v8i32); in AMDGPUTargetLowering()
130 setOperationAction(ISD::LOAD, MVT::v8i64, Promote); in AMDGPUTargetLowering()
131 AddPromotedToType(ISD::LOAD, MVT::v8i64, MVT::v16i32); in AMDGPUTargetLowering()
133 setOperationAction(ISD::LOAD, MVT::v8f64, Promote); in AMDGPUTargetLowering()
134 AddPromotedToType(ISD::LOAD, MVT::v8f64, MVT::v16i32); in AMDGPUTargetLowering()
136 setOperationAction(ISD::LOAD, MVT::v16i64, Promote); in AMDGPUTargetLowering()
137 AddPromotedToType(ISD::LOAD, MVT::v16i64, MVT::v32i32); in AMDGPUTargetLowering()
139 setOperationAction(ISD::LOAD, MVT::v16f64, Promote); in AMDGPUTargetLowering()
140 AddPromotedToType(ISD::LOAD, MVT::v16f64, MVT::v32i32); in AMDGPUTargetLowering()
142 setOperationAction(ISD::LOAD, MVT::i128, Promote); in AMDGPUTargetLowering()
143 AddPromotedToType(ISD::LOAD, MVT::i128, MVT::v4i32); in AMDGPUTargetLowering()
148 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i64, VT, in AMDGPUTargetLowering()
155 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) { in AMDGPUTargetLowering()
166 setLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}, VT, MemVT, in AMDGPUTargetLowering()
169 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in AMDGPUTargetLowering()
170 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::bf16, Expand); in AMDGPUTargetLowering()
171 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
172 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2bf16, Expand); in AMDGPUTargetLowering()
173 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3f16, Expand); in AMDGPUTargetLowering()
174 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3bf16, Expand); in AMDGPUTargetLowering()
175 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in AMDGPUTargetLowering()
176 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4bf16, Expand); in AMDGPUTargetLowering()
177 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
178 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8bf16, Expand); in AMDGPUTargetLowering()
179 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand); in AMDGPUTargetLowering()
180 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16bf16, Expand); in AMDGPUTargetLowering()
181 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
182 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32bf16, Expand); in AMDGPUTargetLowering()
184 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in AMDGPUTargetLowering()
185 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in AMDGPUTargetLowering()
186 setLoadExtAction(ISD::EXTLOAD, MVT::v3f64, MVT::v3f32, Expand); in AMDGPUTargetLowering()
187 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); in AMDGPUTargetLowering()
188 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand); in AMDGPUTargetLowering()
189 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f32, Expand); in AMDGPUTargetLowering()
191 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in AMDGPUTargetLowering()
192 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::bf16, Expand); in AMDGPUTargetLowering()
193 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); in AMDGPUTargetLowering()
194 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2bf16, Expand); in AMDGPUTargetLowering()
195 setLoadExtAction(ISD::EXTLOAD, MVT::v3f64, MVT::v3f16, Expand); in AMDGPUTargetLowering()
196 setLoadExtAction(ISD::EXTLOAD, MVT::v3f64, MVT::v3bf16, Expand); in AMDGPUTargetLowering()
197 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()
198 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4bf16, Expand); in AMDGPUTargetLowering()
199 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand); in AMDGPUTargetLowering()
200 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8bf16, Expand); in AMDGPUTargetLowering()
201 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f16, Expand); in AMDGPUTargetLowering()
202 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16bf16, Expand); in AMDGPUTargetLowering()
204 setOperationAction(ISD::STORE, MVT::f32, Promote); in AMDGPUTargetLowering()
205 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
207 setOperationAction(ISD::STORE, MVT::v2f32, Promote); in AMDGPUTargetLowering()
208 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
210 setOperationAction(ISD::STORE, MVT::v3f32, Promote); in AMDGPUTargetLowering()
211 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
213 setOperationAction(ISD::STORE, MVT::v4f32, Promote); in AMDGPUTargetLowering()
214 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
216 setOperationAction(ISD::STORE, MVT::v5f32, Promote); in AMDGPUTargetLowering()
217 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
219 setOperationAction(ISD::STORE, MVT::v6f32, Promote); in AMDGPUTargetLowering()
220 AddPromotedToType(ISD::STORE, MVT::v6f32, MVT::v6i32); in AMDGPUTargetLowering()
222 setOperationAction(ISD::STORE, MVT::v7f32, Promote); in AMDGPUTargetLowering()
223 AddPromotedToType(ISD::STORE, MVT::v7f32, MVT::v7i32); in AMDGPUTargetLowering()
225 setOperationAction(ISD::STORE, MVT::v8f32, Promote); in AMDGPUTargetLowering()
226 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
228 setOperationAction(ISD::STORE, MVT::v9f32, Promote); in AMDGPUTargetLowering()
229 AddPromotedToType(ISD::STORE, MVT::v9f32, MVT::v9i32); in AMDGPUTargetLowering()
231 setOperationAction(ISD::STORE, MVT::v10f32, Promote); in AMDGPUTargetLowering()
232 AddPromotedToType(ISD::STORE, MVT::v10f32, MVT::v10i32); in AMDGPUTargetLowering()
234 setOperationAction(ISD::STORE, MVT::v11f32, Promote); in AMDGPUTargetLowering()
235 AddPromotedToType(ISD::STORE, MVT::v11f32, MVT::v11i32); in AMDGPUTargetLowering()
237 setOperationAction(ISD::STORE, MVT::v12f32, Promote); in AMDGPUTargetLowering()
238 AddPromotedToType(ISD::STORE, MVT::v12f32, MVT::v12i32); in AMDGPUTargetLowering()
240 setOperationAction(ISD::STORE, MVT::v16f32, Promote); in AMDGPUTargetLowering()
241 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
243 setOperationAction(ISD::STORE, MVT::v32f32, Promote); in AMDGPUTargetLowering()
244 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
246 setOperationAction(ISD::STORE, MVT::i64, Promote); in AMDGPUTargetLowering()
247 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
249 setOperationAction(ISD::STORE, MVT::v2i64, Promote); in AMDGPUTargetLowering()
250 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32); in AMDGPUTargetLowering()
252 setOperationAction(ISD::STORE, MVT::f64, Promote); in AMDGPUTargetLowering()
253 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32); in AMDGPUTargetLowering()
255 setOperationAction(ISD::STORE, MVT::v2f64, Promote); in AMDGPUTargetLowering()
256 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32); in AMDGPUTargetLowering()
258 setOperationAction(ISD::STORE, MVT::v3i64, Promote); in AMDGPUTargetLowering()
259 AddPromotedToType(ISD::STORE, MVT::v3i64, MVT::v6i32); in AMDGPUTargetLowering()
261 setOperationAction(ISD::STORE, MVT::v3f64, Promote); in AMDGPUTargetLowering()
262 AddPromotedToType(ISD::STORE, MVT::v3f64, MVT::v6i32); in AMDGPUTargetLowering()
264 setOperationAction(ISD::STORE, MVT::v4i64, Promote); in AMDGPUTargetLowering()
265 AddPromotedToType(ISD::STORE, MVT::v4i64, MVT::v8i32); in AMDGPUTargetLowering()
267 setOperationAction(ISD::STORE, MVT::v4f64, Promote); in AMDGPUTargetLowering()
268 AddPromotedToType(ISD::STORE, MVT::v4f64, MVT::v8i32); in AMDGPUTargetLowering()
270 setOperationAction(ISD::STORE, MVT::v8i64, Promote); in AMDGPUTargetLowering()
271 AddPromotedToType(ISD::STORE, MVT::v8i64, MVT::v16i32); in AMDGPUTargetLowering()
273 setOperationAction(ISD::STORE, MVT::v8f64, Promote); in AMDGPUTargetLowering()
274 AddPromotedToType(ISD::STORE, MVT::v8f64, MVT::v16i32); in AMDGPUTargetLowering()
276 setOperationAction(ISD::STORE, MVT::v16i64, Promote); in AMDGPUTargetLowering()
277 AddPromotedToType(ISD::STORE, MVT::v16i64, MVT::v32i32); in AMDGPUTargetLowering()
279 setOperationAction(ISD::STORE, MVT::v16f64, Promote); in AMDGPUTargetLowering()
280 AddPromotedToType(ISD::STORE, MVT::v16f64, MVT::v32i32); in AMDGPUTargetLowering()
282 setOperationAction(ISD::STORE, MVT::i128, Promote); in AMDGPUTargetLowering()
283 AddPromotedToType(ISD::STORE, MVT::i128, MVT::v4i32); in AMDGPUTargetLowering()
332 setOperationAction(ISD::Constant, {MVT::i32, MVT::i64}, Legal); in AMDGPUTargetLowering()
333 setOperationAction(ISD::ConstantFP, {MVT::f32, MVT::f64}, Legal); in AMDGPUTargetLowering()
335 setOperationAction({ISD::BR_JT, ISD::BRIND}, MVT::Other, Expand); in AMDGPUTargetLowering()
339 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in AMDGPUTargetLowering()
343 setOperationAction({ISD::FCEIL, ISD::FPOW, ISD::FABS, ISD::FFLOOR, in AMDGPUTargetLowering()
344 ISD::FROUNDEVEN, ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM}, in AMDGPUTargetLowering()
347 setOperationAction(ISD::FLOG2, MVT::f32, Custom); in AMDGPUTargetLowering()
348 setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
351 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
354 setOperationAction(ISD::FNEARBYINT, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
356 setOperationAction(ISD::FRINT, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
358 setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
361 setOperationAction(ISD::IS_FPCLASS, {MVT::f16, MVT::f32, MVT::f64}, Legal); in AMDGPUTargetLowering()
363 setOperationAction(ISD::IS_FPCLASS, {MVT::f32, MVT::f64}, Legal); in AMDGPUTargetLowering()
364 setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Custom); in AMDGPUTargetLowering()
367 setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, in AMDGPUTargetLowering()
374 ISD::IS_FPCLASS, in AMDGPUTargetLowering()
381 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
383 setOperationAction(ISD::CONCAT_VECTORS, in AMDGPUTargetLowering()
393 ISD::EXTRACT_SUBVECTOR, in AMDGPUTargetLowering()
406 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in AMDGPUTargetLowering()
407 setOperationAction(ISD::FP_TO_FP16, {MVT::f64, MVT::f32}, Custom); in AMDGPUTargetLowering()
412 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, VT, in AMDGPUTargetLowering()
416 setOperationAction({ISD::SDIVREM, ISD::UDIVREM}, VT, Custom); in AMDGPUTargetLowering()
419 setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, VT, Expand); in AMDGPUTargetLowering()
421 setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand); in AMDGPUTargetLowering()
424 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal); in AMDGPUTargetLowering()
428 setOperationAction(ISD::FSHR, MVT::i32, Legal); in AMDGPUTargetLowering()
431 setOperationAction(ISD::ROTL, {MVT::i32, MVT::i64}, Expand); in AMDGPUTargetLowering()
432 setOperationAction(ISD::ROTR, MVT::i64, Expand); in AMDGPUTargetLowering()
434 setOperationAction({ISD::MULHU, ISD::MULHS}, MVT::i16, Expand); in AMDGPUTargetLowering()
436 setOperationAction({ISD::MUL, ISD::MULHU, ISD::MULHS}, MVT::i64, Expand); in AMDGPUTargetLowering()
438 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
440 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AMDGPUTargetLowering()
442 setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i32, in AMDGPUTargetLowering()
446 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering()
450 setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, VT, Custom); in AMDGPUTargetLowering()
458 setOperationAction({ISD::ADD, ISD::AND, ISD::FP_TO_SINT, in AMDGPUTargetLowering()
459 ISD::FP_TO_UINT, ISD::MUL, ISD::MULHU, in AMDGPUTargetLowering()
460 ISD::MULHS, ISD::OR, ISD::SHL, in AMDGPUTargetLowering()
461 ISD::SRA, ISD::SRL, ISD::ROTL, in AMDGPUTargetLowering()
462 ISD::ROTR, ISD::SUB, ISD::SINT_TO_FP, in AMDGPUTargetLowering()
463 ISD::UINT_TO_FP, ISD::SDIV, ISD::UDIV, in AMDGPUTargetLowering()
464 ISD::SREM, ISD::UREM, ISD::SMUL_LOHI, in AMDGPUTargetLowering()
465 ISD::UMUL_LOHI, ISD::SDIVREM, ISD::UDIVREM, in AMDGPUTargetLowering()
466 ISD::SELECT, ISD::VSELECT, ISD::SELECT_CC, in AMDGPUTargetLowering()
467 ISD::XOR, ISD::BSWAP, ISD::CTPOP, in AMDGPUTargetLowering()
468 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
469 ISD::SETCC}, in AMDGPUTargetLowering()
479 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, in AMDGPUTargetLowering()
480 ISD::FADD, ISD::FCEIL, ISD::FCOS, in AMDGPUTargetLowering()
481 ISD::FDIV, ISD::FEXP2, ISD::FEXP, in AMDGPUTargetLowering()
482 ISD::FEXP10, ISD::FLOG2, ISD::FREM, in AMDGPUTargetLowering()
483 ISD::FLOG, ISD::FLOG10, ISD::FPOW, in AMDGPUTargetLowering()
484 ISD::FFLOOR, ISD::FTRUNC, ISD::FMUL, in AMDGPUTargetLowering()
485 ISD::FMA, ISD::FRINT, ISD::FNEARBYINT, in AMDGPUTargetLowering()
486 ISD::FSQRT, ISD::FSIN, ISD::FSUB, in AMDGPUTargetLowering()
487 ISD::FNEG, ISD::VSELECT, ISD::SELECT_CC, in AMDGPUTargetLowering()
488 ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE, ISD::SETCC, in AMDGPUTargetLowering()
489 ISD::FCANONICALIZE, ISD::FROUNDEVEN}, in AMDGPUTargetLowering()
496 setOperationAction(ISD::SELECT, MVT::v2f32, Promote); in AMDGPUTargetLowering()
497 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
499 setOperationAction(ISD::SELECT, MVT::v3f32, Promote); in AMDGPUTargetLowering()
500 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
502 setOperationAction(ISD::SELECT, MVT::v4f32, Promote); in AMDGPUTargetLowering()
503 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
505 setOperationAction(ISD::SELECT, MVT::v5f32, Promote); in AMDGPUTargetLowering()
506 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
508 setOperationAction(ISD::SELECT, MVT::v6f32, Promote); in AMDGPUTargetLowering()
509 AddPromotedToType(ISD::SELECT, MVT::v6f32, MVT::v6i32); in AMDGPUTargetLowering()
511 setOperationAction(ISD::SELECT, MVT::v7f32, Promote); in AMDGPUTargetLowering()
512 AddPromotedToType(ISD::SELECT, MVT::v7f32, MVT::v7i32); in AMDGPUTargetLowering()
514 setOperationAction(ISD::SELECT, MVT::v9f32, Promote); in AMDGPUTargetLowering()
515 AddPromotedToType(ISD::SELECT, MVT::v9f32, MVT::v9i32); in AMDGPUTargetLowering()
517 setOperationAction(ISD::SELECT, MVT::v10f32, Promote); in AMDGPUTargetLowering()
518 AddPromotedToType(ISD::SELECT, MVT::v10f32, MVT::v10i32); in AMDGPUTargetLowering()
520 setOperationAction(ISD::SELECT, MVT::v11f32, Promote); in AMDGPUTargetLowering()
521 AddPromotedToType(ISD::SELECT, MVT::v11f32, MVT::v11i32); in AMDGPUTargetLowering()
523 setOperationAction(ISD::SELECT, MVT::v12f32, Promote); in AMDGPUTargetLowering()
524 AddPromotedToType(ISD::SELECT, MVT::v12f32, MVT::v12i32); in AMDGPUTargetLowering()
568 setTargetDAGCombine({ISD::BITCAST, ISD::SHL, in AMDGPUTargetLowering()
569 ISD::SRA, ISD::SRL, in AMDGPUTargetLowering()
570 ISD::TRUNCATE, ISD::MUL, in AMDGPUTargetLowering()
571 ISD::SMUL_LOHI, ISD::UMUL_LOHI, in AMDGPUTargetLowering()
572 ISD::MULHU, ISD::MULHS, in AMDGPUTargetLowering()
573 ISD::SELECT, ISD::SELECT_CC, in AMDGPUTargetLowering()
574 ISD::STORE, ISD::FADD, in AMDGPUTargetLowering()
575 ISD::FSUB, ISD::FNEG, in AMDGPUTargetLowering()
576 ISD::FABS, ISD::AssertZext, in AMDGPUTargetLowering()
577 ISD::AssertSext, ISD::INTRINSIC_WO_CHAIN}); in AMDGPUTargetLowering()
601 case ISD::FADD: in fnegFoldsIntoOpcode()
602 case ISD::FSUB: in fnegFoldsIntoOpcode()
603 case ISD::FMUL: in fnegFoldsIntoOpcode()
604 case ISD::FMA: in fnegFoldsIntoOpcode()
605 case ISD::FMAD: in fnegFoldsIntoOpcode()
606 case ISD::FMINNUM: in fnegFoldsIntoOpcode()
607 case ISD::FMAXNUM: in fnegFoldsIntoOpcode()
608 case ISD::FMINNUM_IEEE: in fnegFoldsIntoOpcode()
609 case ISD::FMAXNUM_IEEE: in fnegFoldsIntoOpcode()
610 case ISD::FMINIMUM: in fnegFoldsIntoOpcode()
611 case ISD::FMAXIMUM: in fnegFoldsIntoOpcode()
612 case ISD::SELECT: in fnegFoldsIntoOpcode()
613 case ISD::FSIN: in fnegFoldsIntoOpcode()
614 case ISD::FTRUNC: in fnegFoldsIntoOpcode()
615 case ISD::FRINT: in fnegFoldsIntoOpcode()
616 case ISD::FNEARBYINT: in fnegFoldsIntoOpcode()
617 case ISD::FROUNDEVEN: in fnegFoldsIntoOpcode()
618 case ISD::FCANONICALIZE: in fnegFoldsIntoOpcode()
629 case ISD::BITCAST: in fnegFoldsIntoOpcode()
638 if (Opc == ISD::BITCAST) { in fnegFoldsIntoOp()
642 if (BCSrc.getOpcode() == ISD::BUILD_VECTOR) { in fnegFoldsIntoOp()
647 return BCSrc.getOpcode() == ISD::SELECT && BCSrc.getValueType() == MVT::f32; in fnegFoldsIntoOp()
658 return (N->getNumOperands() > 2 && N->getOpcode() != ISD::SELECT) || in opMustUseVOP3Encoding()
678 case ISD::CopyToReg: in hasSourceMods()
679 case ISD::FDIV: in hasSourceMods()
680 case ISD::FREM: in hasSourceMods()
681 case ISD::INLINEASM: in hasSourceMods()
682 case ISD::INLINEASM_BR: in hasSourceMods()
684 case ISD::INTRINSIC_W_CHAIN: in hasSourceMods()
689 case ISD::BITCAST: in hasSourceMods()
691 case ISD::INTRINSIC_WO_CHAIN: { in hasSourceMods()
703 case ISD::SELECT: in hasSourceMods()
737 ISD::NodeType ExtendKind) const { in getTypeForExtReturn()
771 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth()
844 case ISD::EntryToken: in isSDNodeAlwaysUniform()
845 case ISD::TokenFactor: in isSDNodeAlwaysUniform()
847 case ISD::INTRINSIC_WO_CHAIN: { in isSDNodeAlwaysUniform()
856 case ISD::LOAD: in isSDNodeAlwaysUniform()
872 case ISD::FMA: in getNegatedExpression()
873 case ISD::FMAD: { in getNegatedExpression()
990 assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA || in isDesirableToCommuteWithShift()
991 N->getOpcode() == ISD::SRL) && in isDesirableToCommuteWithShift()
996 N->getOpcode() != ISD::SHL || N->getOperand(0).getOpcode() != ISD::OR) in isDesirableToCommuteWithShift()
1001 (N->use_begin()->getOpcode() == ISD::SRA || in isDesirableToCommuteWithShift()
1002 N->use_begin()->getOpcode() == ISD::SRL)) in isDesirableToCommuteWithShift()
1007 if (LHS.getOpcode() != ISD::SHL) in isDesirableToCommuteWithShift()
1012 return LHS0 && LHS1 && RHSLd && LHS0->getExtensionType() == ISD::ZEXTLOAD && in isDesirableToCommuteWithShift()
1014 RHSLd->getExtensionType() == ISD::ZEXTLOAD; in isDesirableToCommuteWithShift()
1107 const SmallVectorImpl<ISD::InputArg> &Ins) const { in analyzeFormalArgumentsCompute()
1226 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
1281 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in addTokenForArgument()
1335 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
1336 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1337 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
1338 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
1339 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
1340 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
1341 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
1342 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG); in LowerOperation()
1343 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
1344 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); in LowerOperation()
1345 case ISD::FROUNDEVEN: in LowerOperation()
1347 case ISD::FROUND: return LowerFROUND(Op, DAG); in LowerOperation()
1348 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); in LowerOperation()
1349 case ISD::FLOG2: in LowerOperation()
1351 case ISD::FLOG: in LowerOperation()
1352 case ISD::FLOG10: in LowerOperation()
1354 case ISD::FEXP: in LowerOperation()
1355 case ISD::FEXP10: in LowerOperation()
1357 case ISD::FEXP2: in LowerOperation()
1359 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1360 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
1361 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); in LowerOperation()
1362 case ISD::FP_TO_SINT: in LowerOperation()
1363 case ISD::FP_TO_UINT: in LowerOperation()
1365 case ISD::CTTZ: in LowerOperation()
1366 case ISD::CTTZ_ZERO_UNDEF: in LowerOperation()
1367 case ISD::CTLZ: in LowerOperation()
1368 case ISD::CTLZ_ZERO_UNDEF: in LowerOperation()
1370 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); in LowerOperation()
1379 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1387 case ISD::FLOG2: in ReplaceNodeResults()
1391 case ISD::FLOG: in ReplaceNodeResults()
1392 case ISD::FLOG10: in ReplaceNodeResults()
1396 case ISD::FEXP2: in ReplaceNodeResults()
1400 case ISD::FEXP: in ReplaceNodeResults()
1401 case ISD::FEXP10: in ReplaceNodeResults()
1405 case ISD::CTLZ: in ReplaceNodeResults()
1406 case ISD::CTLZ_ZERO_UNDEF: in ReplaceNodeResults()
1446 SDValue Trap = DAG.getNode(ISD::TRAP, DL, MVT::Other, DAG.getEntryNode()); in LowerGlobalAddress()
1447 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, in LowerGlobalAddress()
1481 SDValue NewIn = DAG.getNode(ISD::BITCAST, SL, NewEltVT, In); in LowerCONCAT_VECTORS()
1491 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1519 SDValue Tmp = DAG.getNode(ISD::BITCAST, SL, NewSrcVT, Op.getOperand(0)); in LowerEXTRACT_SUBVECTOR()
1527 return DAG.getNode(ISD::BITCAST, SL, VT, Tmp); in LowerEXTRACT_SUBVECTOR()
1538 if (Val.getOpcode() == ISD::FNEG) in peekFNeg()
1545 if (Val.getOpcode() == ISD::FNEG) in peekFPSignOps()
1547 if (Val.getOpcode() == ISD::FABS) in peekFPSignOps()
1549 if (Val.getOpcode() == ISD::FCOPYSIGN) in peekFPSignOps()
1558 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in combineFMinMaxLegacyImpl()
1560 case ISD::SETOEQ: in combineFMinMaxLegacyImpl()
1561 case ISD::SETONE: in combineFMinMaxLegacyImpl()
1562 case ISD::SETUNE: in combineFMinMaxLegacyImpl()
1563 case ISD::SETNE: in combineFMinMaxLegacyImpl()
1564 case ISD::SETUEQ: in combineFMinMaxLegacyImpl()
1565 case ISD::SETEQ: in combineFMinMaxLegacyImpl()
1566 case ISD::SETFALSE: in combineFMinMaxLegacyImpl()
1567 case ISD::SETFALSE2: in combineFMinMaxLegacyImpl()
1568 case ISD::SETTRUE: in combineFMinMaxLegacyImpl()
1569 case ISD::SETTRUE2: in combineFMinMaxLegacyImpl()
1570 case ISD::SETUO: in combineFMinMaxLegacyImpl()
1571 case ISD::SETO: in combineFMinMaxLegacyImpl()
1573 case ISD::SETULE: in combineFMinMaxLegacyImpl()
1574 case ISD::SETULT: { in combineFMinMaxLegacyImpl()
1579 case ISD::SETOLE: in combineFMinMaxLegacyImpl()
1580 case ISD::SETOLT: in combineFMinMaxLegacyImpl()
1581 case ISD::SETLE: in combineFMinMaxLegacyImpl()
1582 case ISD::SETLT: { in combineFMinMaxLegacyImpl()
1598 case ISD::SETUGE: in combineFMinMaxLegacyImpl()
1599 case ISD::SETUGT: { in combineFMinMaxLegacyImpl()
1604 case ISD::SETGT: in combineFMinMaxLegacyImpl()
1605 case ISD::SETGE: in combineFMinMaxLegacyImpl()
1606 case ISD::SETOGE: in combineFMinMaxLegacyImpl()
1607 case ISD::SETOGT: { in combineFMinMaxLegacyImpl()
1616 case ISD::SETCC_INVALID: in combineFMinMaxLegacyImpl()
1653 return DAG.getNode(ISD::FNEG, DL, VT, Combined); in combineFMinMaxLegacy()
1665 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1670 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1671 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1679 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
1681 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1687 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getHiHalf64()
1689 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1718 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in splitVector()
1721 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL, in splitVector()
1770 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
1772 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1775 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
1780 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in SplitVectorLoad()
1814 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
1858 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore); in SplitVectorStore()
1887 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
1888 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
1894 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS); in LowerDIVREM24()
1897 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
1901 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT)); in LowerDIVREM24()
1916 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT, in LowerDIVREM24()
1920 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq); in LowerDIVREM24()
1923 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
1935 unsigned OpCode = !Subtarget->hasMadMacF32Insts() ? (unsigned)ISD::FMA in LowerDIVREM24()
1937 : (unsigned)ISD::FMAD; in LowerDIVREM24()
1944 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1947 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
1952 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE); in LowerDIVREM24()
1955 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT)); in LowerDIVREM24()
1958 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq); in LowerDIVREM24()
1961 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS); in LowerDIVREM24()
1962 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem); in LowerDIVREM24()
1968 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); in LowerDIVREM24()
1969 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize); in LowerDIVREM24()
1972 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask); in LowerDIVREM24()
1973 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask); in LowerDIVREM24()
2004 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
2010 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV)); in LowerUDIVREM64()
2011 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM)); in LowerUDIVREM64()
2024 !Subtarget->hasMadMacF32Insts() ? (unsigned)ISD::FMA in LowerUDIVREM64()
2026 ? (unsigned)ISD::FMAD in LowerUDIVREM64()
2029 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo); in LowerUDIVREM64()
2030 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi); in LowerUDIVREM64()
2035 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64()
2037 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1, in LowerUDIVREM64()
2039 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2); in LowerUDIVREM64()
2043 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2); in LowerUDIVREM64()
2044 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc); in LowerUDIVREM64()
2054 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); in LowerUDIVREM64()
2055 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64); in LowerUDIVREM64()
2056 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); in LowerUDIVREM64()
2060 SDValue Add1_Lo = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Rcp_Lo, in LowerUDIVREM64()
2062 SDValue Add1_Hi = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Rcp_Hi, in LowerUDIVREM64()
2068 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1); in LowerUDIVREM64()
2069 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
2073 SDValue Add2_Lo = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Add1_Lo, in LowerUDIVREM64()
2075 SDValue Add2_Hi = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Add1_Hi, in LowerUDIVREM64()
2080 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
2082 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3); in LowerUDIVREM64()
2086 SDValue Sub1_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, LHS_Lo, in LowerUDIVREM64()
2088 SDValue Sub1_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, LHS_Hi, in LowerUDIVREM64()
2090 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64()
2096 ISD::SETUGE); in LowerUDIVREM64()
2098 ISD::SETUGE); in LowerUDIVREM64()
2099 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ); in LowerUDIVREM64()
2106 SDValue Sub2_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub1_Lo, in LowerUDIVREM64()
2108 SDValue Sub2_Mi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
2110 SDValue Sub2_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Mi, in LowerUDIVREM64()
2115 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64); in LowerUDIVREM64()
2118 ISD::SETUGE); in LowerUDIVREM64()
2120 ISD::SETUGE); in LowerUDIVREM64()
2121 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ); in LowerUDIVREM64()
2124 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64); in LowerUDIVREM64()
2126 SDValue Sub3_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Lo, in LowerUDIVREM64()
2128 SDValue Sub3_Mi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Mi, in LowerUDIVREM64()
2130 SDValue Sub3_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub3_Mi, in LowerUDIVREM64()
2138 SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE); in LowerUDIVREM64()
2139 SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE); in LowerUDIVREM64()
2141 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE); in LowerUDIVREM64()
2142 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE); in LowerUDIVREM64()
2152 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
2153 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
2155 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ); in LowerUDIVREM64()
2157 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM); in LowerUDIVREM64()
2159 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ); in LowerUDIVREM64()
2168 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
2169 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One); in LowerUDIVREM64()
2170 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit); in LowerUDIVREM64()
2173 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); in LowerUDIVREM64()
2175 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit); in LowerUDIVREM64()
2178 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
2180 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT); in LowerUDIVREM64()
2183 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS); in LowerUDIVREM64()
2184 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
2188 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV); in LowerUDIVREM64()
2219 SDValue NegY = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Y); in LowerUDIVREM()
2220 SDValue NegYZ = DAG.getNode(ISD::MUL, DL, VT, NegY, Z); in LowerUDIVREM()
2221 Z = DAG.getNode(ISD::ADD, DL, VT, Z, in LowerUDIVREM()
2222 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ)); in LowerUDIVREM()
2225 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z); in LowerUDIVREM()
2227 DAG.getNode(ISD::SUB, DL, VT, X, DAG.getNode(ISD::MUL, DL, VT, Q, Y)); in LowerUDIVREM()
2232 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
2233 Q = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2234 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q); in LowerUDIVREM()
2235 R = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2236 DAG.getNode(ISD::SUB, DL, VT, R, Y), R); in LowerUDIVREM()
2239 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
2240 Q = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2241 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q); in LowerUDIVREM()
2242 R = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2243 DAG.getNode(ISD::SUB, DL, VT, R, Y), R); in LowerUDIVREM()
2270 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero); in LowerSDIVREM()
2271 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero); in LowerSDIVREM()
2272 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
2275 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)), in LowerSDIVREM()
2276 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1)) in LowerSDIVREM()
2281 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
2282 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
2283 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM()
2286 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign); in LowerSDIVREM()
2287 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM()
2289 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign); in LowerSDIVREM()
2290 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
2292 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
2295 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign); in LowerSDIVREM()
2296 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign); in LowerSDIVREM()
2298 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign); in LowerSDIVREM()
2299 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign); in LowerSDIVREM()
2316 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags); in LowerFREM()
2317 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags); in LowerFREM()
2318 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2320 return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags); in LowerFREM()
2331 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2339 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
2340 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFCEIL()
2341 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL()
2343 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
2345 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2357 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in extractF64Exponent()
2381 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
2385 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
2387 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
2391 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2393 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
2400 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
2401 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); in LowerFTRUNC()
2403 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2404 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2406 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2418 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFROUNDEVEN()
2422 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFROUNDEVEN()
2423 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN()
2425 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFROUNDEVEN()
2432 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFROUNDEVEN()
2442 return DAG.getNode(ISD::FROUNDEVEN, SDLoc(Op), Op.getValueType(), in LowerFNEARBYINT()
2449 return DAG.getNode(ISD::FROUNDEVEN, SDLoc(Op), VT, Arg); in LowerFRINT()
2462 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND()
2466 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
2468 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2477 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND()
2478 SDValue OneOrZeroFP = DAG.getNode(ISD::SELECT, SL, VT, Cmp, One, Zero); in LowerFROUND()
2480 SDValue SignedOffset = DAG.getNode(ISD::FCOPYSIGN, SL, VT, OneOrZeroFP, X); in LowerFROUND()
2481 return DAG.getNode(ISD::FADD, SL, VT, T, SignedOffset); in LowerFROUND()
2492 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2500 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
2501 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFFLOOR()
2502 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR()
2504 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
2506 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2512 case ISD::FP_EXTEND: in valueIsKnownNeverF32Denorm()
2514 case ISD::FP16_TO_FP: in valueIsKnownNeverF32Denorm()
2515 case ISD::FFREXP: in valueIsKnownNeverF32Denorm()
2517 case ISD::INTRINSIC_WO_CHAIN: { in valueIsKnownNeverF32Denorm()
2563 SmallestNormal, ISD::SETOLT); in getIsLtSmallestNormal()
2575 SDValue Fabs = DAG.getNode(ISD::FABS, SL, VT, Src, Flags); in getIsFinite()
2578 Inf, ISD::SETOLT); in getIsFinite()
2597 SmallestNormal, ISD::SETOLT); in getScaledLogInput()
2602 DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, Scale32, One, Flags); in getScaledLogInput()
2604 SDValue ScaledInput = DAG.getNode(ISD::FMUL, SL, VT, Src, ScaleFactor, Flags); in getScaledLogInput()
2623 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in LowerFLOG2()
2625 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in LowerFLOG2()
2639 DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, ThirtyTwo, Zero); in LowerFLOG2()
2640 return DAG.getNode(ISD::FSUB, SL, VT, Log2, ResultOffset, Flags); in LowerFLOG2()
2645 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Y, Flags); in getMad()
2646 return DAG.getNode(ISD::FADD, SL, VT, Mul, C, Flags); in getMad()
2656 const bool IsLog10 = Op.getOpcode() == ISD::FLOG10; in LowerFLOGCommon()
2657 assert(IsLog10 || Op.getOpcode() == ISD::FLOG); in LowerFLOGCommon()
2665 X = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, X, Flags); in LowerFLOGCommon()
2670 return DAG.getNode(ISD::FP_ROUND, DL, VT, Lowered, in LowerFLOGCommon()
2696 R = DAG.getNode(ISD::FMUL, DL, VT, Y, C, Flags); in LowerFLOGCommon()
2697 SDValue NegR = DAG.getNode(ISD::FNEG, DL, VT, R, Flags); in LowerFLOGCommon()
2698 SDValue FMA0 = DAG.getNode(ISD::FMA, DL, VT, Y, C, NegR, Flags); in LowerFLOGCommon()
2699 SDValue FMA1 = DAG.getNode(ISD::FMA, DL, VT, Y, CC, FMA0, Flags); in LowerFLOGCommon()
2700 R = DAG.getNode(ISD::FADD, DL, VT, R, FMA1, Flags); in LowerFLOGCommon()
2713 SDValue YAsInt = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Y); in LowerFLOGCommon()
2715 SDValue YHInt = DAG.getNode(ISD::AND, DL, MVT::i32, YAsInt, MaskConst); in LowerFLOGCommon()
2716 SDValue YH = DAG.getNode(ISD::BITCAST, DL, MVT::f32, YHInt); in LowerFLOGCommon()
2717 SDValue YT = DAG.getNode(ISD::FSUB, DL, VT, Y, YH, Flags); in LowerFLOGCommon()
2719 SDValue YTCT = DAG.getNode(ISD::FMUL, DL, VT, YT, CT, Flags); in LowerFLOGCommon()
2731 R = DAG.getNode(ISD::SELECT, DL, VT, IsFinite, R, Y, Flags); in LowerFLOGCommon()
2739 DAG.getNode(ISD::SELECT, DL, VT, IsScaled, ShiftK, Zero, Flags); in LowerFLOGCommon()
2740 R = DAG.getNode(ISD::FSUB, DL, VT, R, Shift, Flags); in LowerFLOGCommon()
2757 VT == MVT::f32 ? (unsigned)AMDGPUISD::LOG : (unsigned)ISD::FLOG2; in LowerFLOGUnsafe()
2771 SDValue ResultOffset = DAG.getNode(ISD::SELECT, SL, VT, IsScaled, in LowerFLOGUnsafe()
2777 return DAG.getNode(ISD::FMA, SL, VT, LogSrc, Log2Inv, ResultOffset, in LowerFLOGUnsafe()
2779 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, LogSrc, Log2Inv, Flags); in LowerFLOGUnsafe()
2780 return DAG.getNode(ISD::FADD, SL, VT, Mul, ResultOffset); in LowerFLOGUnsafe()
2787 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand, in LowerFLOGUnsafe()
2803 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in lowerFEXP2()
2805 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in lowerFEXP2()
2823 DAG.getSetCC(SL, SetCCVT, Src, RangeCheckConst, ISD::SETOLT); in lowerFEXP2()
2829 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, SixtyFour, Zero); in lowerFEXP2()
2831 SDValue AddInput = DAG.getNode(ISD::FADD, SL, VT, Src, AddOffset, Flags); in lowerFEXP2()
2837 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, TwoExpNeg64, One); in lowerFEXP2()
2839 return DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScale, Flags); in lowerFEXP2()
2850 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Log2E, Flags); in lowerFEXPUnsafe()
2852 : (unsigned)ISD::FEXP2, in lowerFEXPUnsafe()
2859 SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT); in lowerFEXPUnsafe()
2863 SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags); in lowerFEXPUnsafe()
2866 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X); in lowerFEXPUnsafe()
2868 SDValue ExpInput = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, Log2E, Flags); in lowerFEXPUnsafe()
2874 DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScaleFactor, Flags); in lowerFEXPUnsafe()
2876 return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, Exp2, in lowerFEXPUnsafe()
2886 const unsigned Exp2Op = VT == MVT::f32 ? AMDGPUISD::EXP : ISD::FEXP2; in lowerFEXP10Unsafe()
2893 SDValue Mul0 = DAG.getNode(ISD::FMUL, SL, VT, X, K0, Flags); in lowerFEXP10Unsafe()
2895 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, X, K1, Flags); in lowerFEXP10Unsafe()
2897 return DAG.getNode(ISD::FMUL, SL, VT, Exp2_0, Exp2_1); in lowerFEXP10Unsafe()
2909 SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT); in lowerFEXP10Unsafe()
2912 SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags); in lowerFEXP10Unsafe()
2914 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X); in lowerFEXP10Unsafe()
2919 SDValue Mul0 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K0, Flags); in lowerFEXP10Unsafe()
2921 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K1, Flags); in lowerFEXP10Unsafe()
2924 SDValue MulExps = DAG.getNode(ISD::FMUL, SL, VT, Exp2_0, Exp2_1, Flags); in lowerFEXP10Unsafe()
2928 DAG.getNode(ISD::FMUL, SL, VT, MulExps, ResultScaleFactor, Flags); in lowerFEXP10Unsafe()
2930 return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, MulExps, in lowerFEXP10Unsafe()
2939 const bool IsExp10 = Op.getOpcode() == ISD::FEXP10; in lowerFEXP()
2953 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, X, Flags); in lowerFEXP()
2955 return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered, in lowerFEXP()
3005 PH = DAG.getNode(ISD::FMUL, SL, VT, X, C, Flags); in lowerFEXP()
3006 SDValue NegPH = DAG.getNode(ISD::FNEG, SL, VT, PH, Flags); in lowerFEXP()
3007 SDValue FMA0 = DAG.getNode(ISD::FMA, SL, VT, X, C, NegPH, Flags); in lowerFEXP()
3008 PL = DAG.getNode(ISD::FMA, SL, VT, X, CC, FMA0, Flags); in lowerFEXP()
3019 SDValue XAsInt = DAG.getNode(ISD::BITCAST, SL, MVT::i32, X); in lowerFEXP()
3021 SDValue XHAsInt = DAG.getNode(ISD::AND, SL, MVT::i32, XAsInt, MaskConst); in lowerFEXP()
3022 SDValue XH = DAG.getNode(ISD::BITCAST, SL, VT, XHAsInt); in lowerFEXP()
3023 SDValue XL = DAG.getNode(ISD::FSUB, SL, VT, X, XH, Flags); in lowerFEXP()
3025 PH = DAG.getNode(ISD::FMUL, SL, VT, XH, CH, Flags); in lowerFEXP()
3027 SDValue XLCL = DAG.getNode(ISD::FMUL, SL, VT, XL, CL, Flags); in lowerFEXP()
3032 SDValue E = DAG.getNode(ISD::FROUNDEVEN, SL, VT, PH, Flags); in lowerFEXP()
3035 SDValue PHSubE = DAG.getNode(ISD::FSUB, SL, VT, PH, E, FlagsNoContract); in lowerFEXP()
3037 SDValue A = DAG.getNode(ISD::FADD, SL, VT, PHSubE, PL, Flags); in lowerFEXP()
3038 SDValue IntE = DAG.getNode(ISD::FP_TO_SINT, SL, MVT::i32, E); in lowerFEXP()
3041 SDValue R = DAG.getNode(ISD::FLDEXP, SL, VT, Exp2, IntE, Flags); in lowerFEXP()
3049 DAG.getSetCC(SL, SetCCVT, X, UnderflowCheckConst, ISD::SETOLT); in lowerFEXP()
3051 R = DAG.getNode(ISD::SELECT, SL, VT, Underflow, Zero, R); in lowerFEXP()
3058 DAG.getSetCC(SL, SetCCVT, X, OverflowCheckConst, ISD::SETOGT); in lowerFEXP()
3061 R = DAG.getNode(ISD::SELECT, SL, VT, Overflow, Inf, R); in lowerFEXP()
3068 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
3072 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF; in isCttzOpc()
3088 auto NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg); in lowerCTLZResults()
3090 NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, ShiftVal); in lowerCTLZResults()
3092 return DAG.getNode(ISD::TRUNCATE, SL, ResultVT, NewOp); in lowerCTLZResults()
3103 bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF || in LowerCTLZ_CTTZ()
3104 Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF; in LowerCTLZ_CTTZ()
3122 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, ConstVal); in LowerCTLZ_CTTZ()
3124 return DAG.getNode(ISD::ZERO_EXTEND, SL, Src.getValueType(), NewOpr); in LowerCTLZ_CTTZ()
3138 unsigned AddOpc = ZeroUndef ? ISD::ADD : ISD::UADDSAT; in LowerCTLZ_CTTZ()
3146 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, OprLo, OprHi); in LowerCTLZ_CTTZ()
3149 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64); in LowerCTLZ_CTTZ()
3152 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr); in LowerCTLZ_CTTZ()
3213 ISD::SRA, SL, MVT::i32, DAG.getNode(ISD::XOR, SL, MVT::i32, Lo, Hi), in LowerINT_TO_FP32()
3216 DAG.getNode(ISD::ADD, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32), in LowerINT_TO_FP32()
3222 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, ShAmt, in LowerINT_TO_FP32()
3224 ShAmt = DAG.getNode(ISD::UMIN, SL, MVT::i32, ShAmt, MaxShAmt); in LowerINT_TO_FP32()
3229 Sign = DAG.getNode(ISD::SRA, SL, MVT::i64, Src, in LowerINT_TO_FP32()
3232 DAG.getNode(ISD::XOR, SL, MVT::i64, in LowerINT_TO_FP32()
3233 DAG.getNode(ISD::ADD, SL, MVT::i64, Src, Sign), Sign); in LowerINT_TO_FP32()
3237 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
3241 SDValue Norm = DAG.getNode(ISD::SHL, SL, MVT::i64, Src, ShAmt); in LowerINT_TO_FP32()
3246 SDValue Adjust = DAG.getNode(ISD::UMIN, SL, MVT::i32, in LowerINT_TO_FP32()
3249 Norm = DAG.getNode(ISD::OR, SL, MVT::i32, Hi, Adjust); in LowerINT_TO_FP32()
3252 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
3257 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32), in LowerINT_TO_FP32()
3261 return DAG.getNode(ISD::FLDEXP, SL, MVT::f32, FVal, ShAmt); in LowerINT_TO_FP32()
3266 SDValue Exp = DAG.getNode(ISD::SHL, SL, MVT::i32, ShAmt, in LowerINT_TO_FP32()
3269 DAG.getNode(ISD::ADD, SL, MVT::i32, in LowerINT_TO_FP32()
3270 DAG.getNode(ISD::BITCAST, SL, MVT::i32, FVal), Exp); in LowerINT_TO_FP32()
3273 Sign = DAG.getNode(ISD::SHL, SL, MVT::i32, in LowerINT_TO_FP32()
3274 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Sign), in LowerINT_TO_FP32()
3276 IVal = DAG.getNode(ISD::OR, SL, MVT::i32, IVal, Sign); in LowerINT_TO_FP32()
3278 return DAG.getNode(ISD::BITCAST, SL, MVT::f32, IVal); in LowerINT_TO_FP32()
3289 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
3292 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
3294 SDValue LdExp = DAG.getNode(ISD::FLDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
3297 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
3313 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src); in LowerUINT_TO_FP()
3314 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
3319 SDValue ToF32 = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f32, Src); in LowerUINT_TO_FP()
3321 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerUINT_TO_FP()
3334 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
3359 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, Src); in LowerSINT_TO_FP()
3360 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext); in LowerSINT_TO_FP()
3365 SDValue ToF32 = DAG.getNode(ISD::SINT_TO_FP, SL, MVT::f32, Src); in LowerSINT_TO_FP()
3367 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerSINT_TO_FP()
3383 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3413 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src); in LowerFP_TO_INT64()
3421 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32, in LowerFP_TO_INT64()
3422 DAG.getNode(ISD::BITCAST, SL, MVT::i32, Trunc), in LowerFP_TO_INT64()
3424 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
3442 SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0); in LowerFP_TO_INT64()
3444 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
3446 SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc); in LowerFP_TO_INT64()
3448 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
3449 : ISD::FP_TO_UINT, in LowerFP_TO_INT64()
3451 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP_TO_INT64()
3453 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
3459 Sign = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
3463 DAG.getNode(ISD::SUB, SL, MVT::i64, in LowerFP_TO_INT64()
3464 DAG.getNode(ISD::XOR, SL, MVT::i64, Result, Sign), Sign); in LowerFP_TO_INT64()
3491 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0); in LowerFP_TO_FP16()
3492 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
3496 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3498 E = DAG.getNode(ISD::AND, DL, MVT::i32, E, in LowerFP_TO_FP16()
3502 E = DAG.getNode(ISD::ADD, DL, MVT::i32, E, in LowerFP_TO_FP16()
3505 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3507 M = DAG.getNode(ISD::AND, DL, MVT::i32, M, in LowerFP_TO_FP16()
3510 SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3512 MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U); in LowerFP_TO_FP16()
3514 SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ); in LowerFP_TO_FP16()
3515 M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set); in LowerFP_TO_FP16()
3518 SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32, in LowerFP_TO_FP16()
3520 Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32)); in LowerFP_TO_FP16()
3523 SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M, in LowerFP_TO_FP16()
3524 DAG.getNode(ISD::SHL, DL, MVT::i32, E, in LowerFP_TO_FP16()
3528 SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32, in LowerFP_TO_FP16()
3530 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero); in LowerFP_TO_FP16()
3531 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B, in LowerFP_TO_FP16()
3534 SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M, in LowerFP_TO_FP16()
3537 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerFP_TO_FP16()
3538 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B); in LowerFP_TO_FP16()
3539 SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE); in LowerFP_TO_FP16()
3540 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1); in LowerFP_TO_FP16()
3542 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT); in LowerFP_TO_FP16()
3543 SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V, in LowerFP_TO_FP16()
3545 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
3548 One, Zero, ISD::SETEQ); in LowerFP_TO_FP16()
3550 One, Zero, ISD::SETGT); in LowerFP_TO_FP16()
3551 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1); in LowerFP_TO_FP16()
3552 V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1); in LowerFP_TO_FP16()
3555 DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT); in LowerFP_TO_FP16()
3557 I, V, ISD::SETEQ); in LowerFP_TO_FP16()
3560 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3562 Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign, in LowerFP_TO_FP16()
3565 V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V); in LowerFP_TO_FP16()
3582 SDValue PromotedSrc = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src); in LowerFP_TO_INT()
3591 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToInt32); in LowerFP_TO_INT()
3598 (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) { in LowerFP_TO_INT()
3603 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT()
3608 return LowerFP_TO_INT64(Op, DAG, OpOpcode == ISD::FP_TO_SINT); in LowerFP_TO_INT()
3631 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp); in LowerSIGN_EXTEND_INREG()
3655 bool IsIntrin = Node24->getOpcode() == ISD::INTRINSIC_WO_CHAIN; in simplifyMul24()
3752 if (!LN->isSimple() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN)) in performLoadCombine()
3792 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad); in performLoadCombine()
3805 if (!SN->isSimple() || !ISD::isNormalStore(SN)) in performStoreCombine()
3843 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
3845 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal); in performStoreCombine()
3863 if (N0.getOpcode() == ISD::TRUNCATE) { in performAssertSZExtCombine()
3872 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg); in performAssertSZExtCombine()
3935 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in splitBinaryBitConstantOpImpl()
3957 case ISD::ZERO_EXTEND: in performShlCombine()
3958 case ISD::SIGN_EXTEND: in performShlCombine()
3959 case ISD::ANY_EXTEND: { in performShlCombine()
3963 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) { in performShlCombine()
3968 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec); in performShlCombine()
3979 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
3997 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
3998 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine()
4003 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performShlCombine()
4022 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
4026 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
4032 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
4035 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
4055 if (LHS.getOpcode() == ISD::AND) { in performSrlCombine()
4061 ISD::AND, SL, VT, in performSrlCombine()
4062 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)), in performSrlCombine()
4063 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1))); in performSrlCombine()
4082 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
4086 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair); in performSrlCombine()
4097 if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) { in performTruncateCombine()
4099 if (Vec.getOpcode() == ISD::BUILD_VECTOR) { in performTruncateCombine()
4104 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
4108 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
4116 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) { in performTruncateCombine()
4120 if (BV.getOpcode() == ISD::BUILD_VECTOR && in performTruncateCombine()
4125 SrcElt = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
4129 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()
4142 (Src.getOpcode() == ISD::SRL || in performTruncateCombine()
4143 Src.getOpcode() == ISD::SRA || in performTruncateCombine()
4144 Src.getOpcode() == ISD::SHL)) { in performTruncateCombine()
4153 (Src.getOpcode() == ISD::SHL) ? 31 : (32 - VT.getScalarSizeInBits()); in performTruncateCombine()
4160 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
4171 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift); in performTruncateCombine()
4196 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, MulLo, MulHi); in getMul24()
4202 if (V->getOpcode() != ISD::ADD) in getAddOneOp()
4239 return U->getOpcode() == ISD::MUL; in performMulCombine()
4250 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N1); in performMulCombine()
4255 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N0); in performMulCombine()
4259 if (N->getOpcode() != ISD::MUL) in performMulCombine()
4270 if (N0.getOpcode() == ISD::ANY_EXTEND) in performMulCombine()
4273 if (N1.getOpcode() == ISD::ANY_EXTEND) in performMulCombine()
4311 if (N0.getOpcode() == ISD::ANY_EXTEND) in performMulLoHiCombine()
4313 if (N1.getOpcode() == ISD::ANY_EXTEND) in performMulLoHiCombine()
4416 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op); in getFFBX_U32()
4420 FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX); in getFFBX_U32()
4439 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); in performCtlz_CttzCombine()
4444 if (CCOpcode == ISD::SETEQ && in performCtlz_CttzCombine()
4454 if (CCOpcode == ISD::SETNE && in performCtlz_CttzCombine()
4475 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond, in distributeOpThroughSelect()
4497 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) || in foldFreeOpFromSelect()
4498 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
4507 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
4514 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS && in foldFreeOpFromSelect()
4527 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(NewLHS.getNode())) in foldFreeOpFromSelect()
4529 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL) in foldFreeOpFromSelect()
4534 if (LHS.getOpcode() == ISD::FABS && CRHS->isNegative()) in foldFreeOpFromSelect()
4543 if (NewLHS.getOpcode() == ISD::FABS && in foldFreeOpFromSelect()
4550 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
4551 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
4556 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, in foldFreeOpFromSelect()
4572 if (Cond.getOpcode() != ISD::SETCC) in performSelectCombine()
4592 ISD::CondCode NewCC = in performSelectCombine()
4596 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True); in performSelectCombine()
4649 case ISD::FMAXNUM: in inverseMinMax()
4650 return ISD::FMINNUM; in inverseMinMax()
4651 case ISD::FMINNUM: in inverseMinMax()
4652 return ISD::FMAXNUM; in inverseMinMax()
4653 case ISD::FMAXNUM_IEEE: in inverseMinMax()
4654 return ISD::FMINNUM_IEEE; in inverseMinMax()
4655 case ISD::FMINNUM_IEEE: in inverseMinMax()
4656 return ISD::FMAXNUM_IEEE; in inverseMinMax()
4657 case ISD::FMAXIMUM: in inverseMinMax()
4658 return ISD::FMINIMUM; in inverseMinMax()
4659 case ISD::FMINIMUM: in inverseMinMax()
4660 return ISD::FMAXIMUM; in inverseMinMax()
4704 case ISD::FADD: { in performFNegCombine()
4712 if (LHS.getOpcode() != ISD::FNEG) in performFNegCombine()
4713 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
4717 if (RHS.getOpcode() != ISD::FNEG) in performFNegCombine()
4718 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4722 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4723 if (Res.getOpcode() != ISD::FADD) in performFNegCombine()
4726 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4729 case ISD::FMUL: in performFNegCombine()
4736 if (LHS.getOpcode() == ISD::FNEG) in performFNegCombine()
4738 else if (RHS.getOpcode() == ISD::FNEG) in performFNegCombine()
4741 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4747 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4750 case ISD::FMA: in performFNegCombine()
4751 case ISD::FMAD: { in performFNegCombine()
4761 if (LHS.getOpcode() == ISD::FNEG) in performFNegCombine()
4763 else if (MHS.getOpcode() == ISD::FNEG) in performFNegCombine()
4766 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS); in performFNegCombine()
4768 if (RHS.getOpcode() != ISD::FNEG) in performFNegCombine()
4769 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4777 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4780 case ISD::FMAXNUM: in performFNegCombine()
4781 case ISD::FMINNUM: in performFNegCombine()
4782 case ISD::FMAXNUM_IEEE: in performFNegCombine()
4783 case ISD::FMINNUM_IEEE: in performFNegCombine()
4784 case ISD::FMINIMUM: in performFNegCombine()
4785 case ISD::FMAXIMUM: in performFNegCombine()
4801 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
4802 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4809 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4815 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
4822 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Res); in performFNegCombine()
4831 case ISD::FP_EXTEND: in performFNegCombine()
4832 case ISD::FTRUNC: in performFNegCombine()
4833 case ISD::FRINT: in performFNegCombine()
4834 case ISD::FNEARBYINT: // XXX - Should fround be handled? in performFNegCombine()
4835 case ISD::FROUNDEVEN: in performFNegCombine()
4836 case ISD::FSIN: in performFNegCombine()
4837 case ISD::FCANONICALIZE: in performFNegCombine()
4843 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine()
4854 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
4857 case ISD::FP_ROUND: { in performFNegCombine()
4860 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine()
4862 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
4870 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
4871 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
4873 case ISD::FP16_TO_FP: { in performFNegCombine()
4883 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src, in performFNegCombine()
4885 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg); in performFNegCombine()
4887 case ISD::SELECT: { in performFNegCombine()
4892 case ISD::BITCAST: { in performFNegCombine()
4895 if (BCSrc.getOpcode() == ISD::BUILD_VECTOR) { in performFNegCombine()
4910 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::f32, HighBits); in performFNegCombine()
4911 SDValue NegHi = DAG.getNode(ISD::FNEG, SL, MVT::f32, CastHi); in performFNegCombine()
4913 DAG.getNode(ISD::BITCAST, SL, HighBits.getValueType(), NegHi); in performFNegCombine()
4919 DAG.getNode(ISD::BUILD_VECTOR, SL, BCSrc.getValueType(), Ops); in performFNegCombine()
4920 SDValue Result = DAG.getNode(ISD::BITCAST, SL, VT, Build); in performFNegCombine()
4923 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Result)); in performFNegCombine()
4927 if (BCSrc.getOpcode() == ISD::SELECT && VT == MVT::f32 && in performFNegCombine()
4935 DAG.getNode(ISD::BITCAST, SL, MVT::f32, BCSrc.getOperand(1)); in performFNegCombine()
4937 DAG.getNode(ISD::BITCAST, SL, MVT::f32, BCSrc.getOperand(2)); in performFNegCombine()
4939 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, LHS); in performFNegCombine()
4940 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHS); in performFNegCombine()
4942 return DAG.getNode(ISD::SELECT, SL, MVT::f32, BCSrc.getOperand(0), NegLHS, in performFNegCombine()
4962 case ISD::FP16_TO_FP: { in performFAbsCombine()
4969 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src, in performFAbsCombine()
4971 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs); in performFAbsCombine()
4998 case ISD::BITCAST: { in PerformDAGCombine()
5008 if (Src.getOpcode() == ISD::BUILD_VECTOR && in PerformDAGCombine()
5010 isOperationLegal(ISD::BUILD_VECTOR, DestVT))) { in PerformDAGCombine()
5021 CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt)); in PerformDAGCombine()
5040 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
5043 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV); in PerformDAGCombine()
5050 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
5054 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec); in PerformDAGCombine()
5059 case ISD::SHL: { in PerformDAGCombine()
5065 case ISD::SRL: { in PerformDAGCombine()
5071 case ISD::SRA: { in PerformDAGCombine()
5077 case ISD::TRUNCATE: in PerformDAGCombine()
5079 case ISD::MUL: in PerformDAGCombine()
5090 case ISD::SMUL_LOHI: in PerformDAGCombine()
5091 case ISD::UMUL_LOHI: in PerformDAGCombine()
5093 case ISD::MULHS: in PerformDAGCombine()
5095 case ISD::MULHU: in PerformDAGCombine()
5097 case ISD::SELECT: in PerformDAGCombine()
5099 case ISD::FNEG: in PerformDAGCombine()
5101 case ISD::FABS: in PerformDAGCombine()
5140 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
5166 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, in PerformDAGCombine()
5187 case ISD::LOAD: in PerformDAGCombine()
5189 case ISD::STORE: in PerformDAGCombine()
5194 case ISD::AssertZext: in PerformDAGCombine()
5195 case ISD::AssertSext: in PerformDAGCombine()
5197 case ISD::INTRINSIC_WO_CHAIN: in PerformDAGCombine()
5302 Ptr = DAG.getNode(ISD::ADD, SL, MVT::i32, SP, Ptr); in storeStackInputValue()
5323 V = DAG.getNode(ISD::SRL, SL, VT, V, in loadInputValue()
5325 return DAG.getNode(ISD::AND, SL, VT, V, in loadInputValue()
5719 case ISD::INTRINSIC_WO_CHAIN: { in computeKnownBitsForTargetNode()
5885 case ISD::FLDEXP: in isKnownNeverNaNForTargetNode()
5901 case ISD::INTRINSIC_WO_CHAIN: { in isKnownNeverNaNForTargetNode()