Lines Matching refs:ISD
143 bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { in isConstantSplatVector()
144 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
178 bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) { in isConstantSplatVectorAllOnes()
180 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllOnes()
183 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllOnes()
188 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllOnes()
227 bool ISD::isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly) { in isConstantSplatVectorAllZeros()
229 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllZeros()
232 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllZeros()
237 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllZeros()
269 bool ISD::isBuildVectorAllOnes(const SDNode *N) { in isBuildVectorAllOnes()
273 bool ISD::isBuildVectorAllZeros(const SDNode *N) { in isBuildVectorAllZeros()
277 bool ISD::isBuildVectorOfConstantSDNodes(const SDNode *N) { in isBuildVectorOfConstantSDNodes()
278 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantSDNodes()
290 bool ISD::isBuildVectorOfConstantFPSDNodes(const SDNode *N) { in isBuildVectorOfConstantFPSDNodes()
291 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantFPSDNodes()
303 bool ISD::isVectorShrinkable(const SDNode *N, unsigned NewEltSize, in isVectorShrinkable()
311 if (N->getOpcode() == ISD::ZERO_EXTEND) { in isVectorShrinkable()
316 if (N->getOpcode() == ISD::SIGN_EXTEND) { in isVectorShrinkable()
321 if (N->getOpcode() != ISD::BUILD_VECTOR) in isVectorShrinkable()
340 bool ISD::allOperandsUndef(const SDNode *N) { in allOperandsUndef()
349 bool ISD::isFreezeUndef(const SDNode *N) { in isFreezeUndef()
350 return N->getOpcode() == ISD::FREEZE && N->getOperand(0).isUndef(); in isFreezeUndef()
354 bool ISD::matchUnaryPredicateImpl(SDValue Op, in matchUnaryPredicateImpl()
362 if (ISD::BUILD_VECTOR != Op.getOpcode() && in matchUnaryPredicateImpl()
363 ISD::SPLAT_VECTOR != Op.getOpcode()) in matchUnaryPredicateImpl()
381 template bool ISD::matchUnaryPredicateImpl<ConstantSDNode>(
383 template bool ISD::matchUnaryPredicateImpl<ConstantFPSDNode>(
386 bool ISD::matchBinaryPredicate( in matchBinaryPredicate()
400 (LHS.getOpcode() != ISD::BUILD_VECTOR && in matchBinaryPredicate()
401 LHS.getOpcode() != ISD::SPLAT_VECTOR)) in matchBinaryPredicate()
423 ISD::NodeType ISD::getVecReduceBaseOpcode(unsigned VecReduceOpcode) { in getVecReduceBaseOpcode()
427 case ISD::VECREDUCE_FADD: in getVecReduceBaseOpcode()
428 case ISD::VECREDUCE_SEQ_FADD: in getVecReduceBaseOpcode()
429 case ISD::VP_REDUCE_FADD: in getVecReduceBaseOpcode()
430 case ISD::VP_REDUCE_SEQ_FADD: in getVecReduceBaseOpcode()
431 return ISD::FADD; in getVecReduceBaseOpcode()
432 case ISD::VECREDUCE_FMUL: in getVecReduceBaseOpcode()
433 case ISD::VECREDUCE_SEQ_FMUL: in getVecReduceBaseOpcode()
434 case ISD::VP_REDUCE_FMUL: in getVecReduceBaseOpcode()
435 case ISD::VP_REDUCE_SEQ_FMUL: in getVecReduceBaseOpcode()
436 return ISD::FMUL; in getVecReduceBaseOpcode()
437 case ISD::VECREDUCE_ADD: in getVecReduceBaseOpcode()
438 case ISD::VP_REDUCE_ADD: in getVecReduceBaseOpcode()
439 return ISD::ADD; in getVecReduceBaseOpcode()
440 case ISD::VECREDUCE_MUL: in getVecReduceBaseOpcode()
441 case ISD::VP_REDUCE_MUL: in getVecReduceBaseOpcode()
442 return ISD::MUL; in getVecReduceBaseOpcode()
443 case ISD::VECREDUCE_AND: in getVecReduceBaseOpcode()
444 case ISD::VP_REDUCE_AND: in getVecReduceBaseOpcode()
445 return ISD::AND; in getVecReduceBaseOpcode()
446 case ISD::VECREDUCE_OR: in getVecReduceBaseOpcode()
447 case ISD::VP_REDUCE_OR: in getVecReduceBaseOpcode()
448 return ISD::OR; in getVecReduceBaseOpcode()
449 case ISD::VECREDUCE_XOR: in getVecReduceBaseOpcode()
450 case ISD::VP_REDUCE_XOR: in getVecReduceBaseOpcode()
451 return ISD::XOR; in getVecReduceBaseOpcode()
452 case ISD::VECREDUCE_SMAX: in getVecReduceBaseOpcode()
453 case ISD::VP_REDUCE_SMAX: in getVecReduceBaseOpcode()
454 return ISD::SMAX; in getVecReduceBaseOpcode()
455 case ISD::VECREDUCE_SMIN: in getVecReduceBaseOpcode()
456 case ISD::VP_REDUCE_SMIN: in getVecReduceBaseOpcode()
457 return ISD::SMIN; in getVecReduceBaseOpcode()
458 case ISD::VECREDUCE_UMAX: in getVecReduceBaseOpcode()
459 case ISD::VP_REDUCE_UMAX: in getVecReduceBaseOpcode()
460 return ISD::UMAX; in getVecReduceBaseOpcode()
461 case ISD::VECREDUCE_UMIN: in getVecReduceBaseOpcode()
462 case ISD::VP_REDUCE_UMIN: in getVecReduceBaseOpcode()
463 return ISD::UMIN; in getVecReduceBaseOpcode()
464 case ISD::VECREDUCE_FMAX: in getVecReduceBaseOpcode()
465 case ISD::VP_REDUCE_FMAX: in getVecReduceBaseOpcode()
466 return ISD::FMAXNUM; in getVecReduceBaseOpcode()
467 case ISD::VECREDUCE_FMIN: in getVecReduceBaseOpcode()
468 case ISD::VP_REDUCE_FMIN: in getVecReduceBaseOpcode()
469 return ISD::FMINNUM; in getVecReduceBaseOpcode()
470 case ISD::VECREDUCE_FMAXIMUM: in getVecReduceBaseOpcode()
471 return ISD::FMAXIMUM; in getVecReduceBaseOpcode()
472 case ISD::VECREDUCE_FMINIMUM: in getVecReduceBaseOpcode()
473 return ISD::FMINIMUM; in getVecReduceBaseOpcode()
477 bool ISD::isVPOpcode(unsigned Opcode) { in isVPOpcode()
482 case ISD::VPSD: \ in isVPOpcode()
488 bool ISD::isVPBinaryOp(unsigned Opcode) { in isVPBinaryOp()
492 #define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD: in isVPBinaryOp()
500 bool ISD::isVPReduction(unsigned Opcode) { in isVPReduction()
504 #define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD: in isVPReduction()
513 std::optional<unsigned> ISD::getVPMaskIdx(unsigned Opcode) { in getVPMaskIdx()
518 case ISD::VPSD: \ in getVPMaskIdx()
525 std::optional<unsigned> ISD::getVPExplicitVectorLengthIdx(unsigned Opcode) { in getVPExplicitVectorLengthIdx()
530 case ISD::VPSD: \ in getVPExplicitVectorLengthIdx()
536 std::optional<unsigned> ISD::getBaseOpcodeForVP(unsigned VPOpcode, in getBaseOpcodeForVP()
542 #define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) case ISD::VPOPC: in getBaseOpcodeForVP()
543 #define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) return ISD::SDOPC; in getBaseOpcodeForVP()
550 unsigned ISD::getVPForBaseOpcode(unsigned Opcode) { in getVPForBaseOpcode()
555 #define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) case ISD::SDOPC: in getVPForBaseOpcode()
556 #define END_REGISTER_VP_SDNODE(VPOPC) return ISD::VPOPC; in getVPForBaseOpcode()
561 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType()
563 case ISD::EXTLOAD: in getExtForLoadExtType()
564 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
565 case ISD::SEXTLOAD: in getExtForLoadExtType()
566 return ISD::SIGN_EXTEND; in getExtForLoadExtType()
567 case ISD::ZEXTLOAD: in getExtForLoadExtType()
568 return ISD::ZERO_EXTEND; in getExtForLoadExtType()
576 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { in getSetCCSwappedOperands()
581 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits in getSetCCSwappedOperands()
586 static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike) { in getSetCCInverseImpl()
593 if (Operation > ISD::SETTRUE2) in getSetCCInverseImpl()
596 return ISD::CondCode(Operation); in getSetCCInverseImpl()
599 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, EVT Type) { in getSetCCInverse()
603 ISD::CondCode ISD::GlobalISel::getSetCCInverse(ISD::CondCode Op, in getSetCCInverse()
611 static int isSignedOp(ISD::CondCode Opcode) { in isSignedOp()
614 case ISD::SETEQ: in isSignedOp()
615 case ISD::SETNE: return 0; in isSignedOp()
616 case ISD::SETLT: in isSignedOp()
617 case ISD::SETLE: in isSignedOp()
618 case ISD::SETGT: in isSignedOp()
619 case ISD::SETGE: return 1; in isSignedOp()
620 case ISD::SETULT: in isSignedOp()
621 case ISD::SETULE: in isSignedOp()
622 case ISD::SETUGT: in isSignedOp()
623 case ISD::SETUGE: return 2; in isSignedOp()
627 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
632 return ISD::SETCC_INVALID; in getSetCCOrOperation()
638 if (Op > ISD::SETTRUE2) in getSetCCOrOperation()
642 if (IsInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT in getSetCCOrOperation()
643 Op = ISD::SETNE; in getSetCCOrOperation()
645 return ISD::CondCode(Op); in getSetCCOrOperation()
648 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
653 return ISD::SETCC_INVALID; in getSetCCAndOperation()
656 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
662 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT in getSetCCAndOperation()
663 case ISD::SETOEQ: // SETEQ & SETU[LG]E in getSetCCAndOperation()
664 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE in getSetCCAndOperation()
665 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE in getSetCCAndOperation()
666 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE in getSetCCAndOperation()
716 case ISD::TargetExternalSymbol: in AddNodeIDCustom()
717 case ISD::ExternalSymbol: in AddNodeIDCustom()
718 case ISD::MCSymbol: in AddNodeIDCustom()
721 case ISD::TargetConstant: in AddNodeIDCustom()
722 case ISD::Constant: { in AddNodeIDCustom()
728 case ISD::TargetConstantFP: in AddNodeIDCustom()
729 case ISD::ConstantFP: in AddNodeIDCustom()
732 case ISD::TargetGlobalAddress: in AddNodeIDCustom()
733 case ISD::GlobalAddress: in AddNodeIDCustom()
734 case ISD::TargetGlobalTLSAddress: in AddNodeIDCustom()
735 case ISD::GlobalTLSAddress: { in AddNodeIDCustom()
742 case ISD::BasicBlock: in AddNodeIDCustom()
745 case ISD::Register: in AddNodeIDCustom()
748 case ISD::RegisterMask: in AddNodeIDCustom()
751 case ISD::SRCVALUE: in AddNodeIDCustom()
754 case ISD::FrameIndex: in AddNodeIDCustom()
755 case ISD::TargetFrameIndex: in AddNodeIDCustom()
758 case ISD::LIFETIME_START: in AddNodeIDCustom()
759 case ISD::LIFETIME_END: in AddNodeIDCustom()
765 case ISD::PSEUDO_PROBE: in AddNodeIDCustom()
770 case ISD::JumpTable: in AddNodeIDCustom()
771 case ISD::TargetJumpTable: in AddNodeIDCustom()
775 case ISD::ConstantPool: in AddNodeIDCustom()
776 case ISD::TargetConstantPool: { in AddNodeIDCustom()
787 case ISD::TargetIndex: { in AddNodeIDCustom()
794 case ISD::LOAD: { in AddNodeIDCustom()
802 case ISD::STORE: { in AddNodeIDCustom()
810 case ISD::VP_LOAD: { in AddNodeIDCustom()
818 case ISD::VP_STORE: { in AddNodeIDCustom()
826 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: { in AddNodeIDCustom()
833 case ISD::EXPERIMENTAL_VP_STRIDED_STORE: { in AddNodeIDCustom()
840 case ISD::VP_GATHER: { in AddNodeIDCustom()
848 case ISD::VP_SCATTER: { in AddNodeIDCustom()
856 case ISD::MLOAD: { in AddNodeIDCustom()
864 case ISD::MSTORE: { in AddNodeIDCustom()
872 case ISD::MGATHER: { in AddNodeIDCustom()
880 case ISD::MSCATTER: { in AddNodeIDCustom()
888 case ISD::ATOMIC_CMP_SWAP: in AddNodeIDCustom()
889 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: in AddNodeIDCustom()
890 case ISD::ATOMIC_SWAP: in AddNodeIDCustom()
891 case ISD::ATOMIC_LOAD_ADD: in AddNodeIDCustom()
892 case ISD::ATOMIC_LOAD_SUB: in AddNodeIDCustom()
893 case ISD::ATOMIC_LOAD_AND: in AddNodeIDCustom()
894 case ISD::ATOMIC_LOAD_CLR: in AddNodeIDCustom()
895 case ISD::ATOMIC_LOAD_OR: in AddNodeIDCustom()
896 case ISD::ATOMIC_LOAD_XOR: in AddNodeIDCustom()
897 case ISD::ATOMIC_LOAD_NAND: in AddNodeIDCustom()
898 case ISD::ATOMIC_LOAD_MIN: in AddNodeIDCustom()
899 case ISD::ATOMIC_LOAD_MAX: in AddNodeIDCustom()
900 case ISD::ATOMIC_LOAD_UMIN: in AddNodeIDCustom()
901 case ISD::ATOMIC_LOAD_UMAX: in AddNodeIDCustom()
902 case ISD::ATOMIC_LOAD: in AddNodeIDCustom()
903 case ISD::ATOMIC_STORE: { in AddNodeIDCustom()
911 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
918 case ISD::TargetBlockAddress: in AddNodeIDCustom()
919 case ISD::BlockAddress: { in AddNodeIDCustom()
926 case ISD::AssertAlign: in AddNodeIDCustom()
929 case ISD::PREFETCH: in AddNodeIDCustom()
930 case ISD::INTRINSIC_VOID: in AddNodeIDCustom()
931 case ISD::INTRINSIC_W_CHAIN: in AddNodeIDCustom()
970 case ISD::HANDLENODE: in doNotCSE()
971 case ISD::EH_LABEL: in doNotCSE()
1014 if (N->getOpcode() == ISD::DELETED_NODE) in RemoveDeadNodes()
1101 N->NodeType = ISD::DELETED_NODE; in DeallocateNode()
1117 case ISD::BUILD_PAIR: { in VerifySDNode()
1131 case ISD::BUILD_VECTOR: { in VerifySDNode()
1172 case ISD::HANDLENODE: return false; // noop. in RemoveNodeFromCSEMaps()
1173 case ISD::CONDCODE: in RemoveNodeFromCSEMaps()
1179 case ISD::ExternalSymbol: in RemoveNodeFromCSEMaps()
1182 case ISD::TargetExternalSymbol: { in RemoveNodeFromCSEMaps()
1188 case ISD::MCSymbol: { in RemoveNodeFromCSEMaps()
1193 case ISD::VALUETYPE: { in RemoveNodeFromCSEMaps()
1205 assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!"); in RemoveNodeFromCSEMaps()
1206 assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!"); in RemoveNodeFromCSEMaps()
1319 : TM(tm), OptLevel(OL), EntryNode(ISD::EntryToken, 0, DebugLoc(), in SelectionDAG()
1373 case ISD::Constant: in FindNodeOrInsertPos()
1374 case ISD::ConstantFP: in FindNodeOrInsertPos()
1387 case ISD::Constant: in FindNodeOrInsertPos()
1388 case ISD::ConstantFP: in FindNodeOrInsertPos()
1431 ? getNode(ISD::FP_EXTEND, DL, VT, Op) in getFPExtendOrRound()
1432 : getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtendOrRound()
1443 ? getNode(ISD::STRICT_FP_EXTEND, DL, {VT, MVT::Other}, {Chain, Op}) in getStrictFPExtendOrRound()
1444 : getNode(ISD::STRICT_FP_ROUND, DL, {VT, MVT::Other}, in getStrictFPExtendOrRound()
1452 getNode(ISD::ANY_EXTEND, DL, VT, Op) : in getAnyExtOrTrunc()
1453 getNode(ISD::TRUNCATE, DL, VT, Op); in getAnyExtOrTrunc()
1458 getNode(ISD::SIGN_EXTEND, DL, VT, Op) : in getSExtOrTrunc()
1459 getNode(ISD::TRUNCATE, DL, VT, Op); in getSExtOrTrunc()
1464 getNode(ISD::ZERO_EXTEND, DL, VT, Op) : in getZExtOrTrunc()
1465 getNode(ISD::TRUNCATE, DL, VT, Op); in getZExtOrTrunc()
1516 return getNode(ISD::TRUNCATE, SL, VT, Op); in getBoolExtOrTrunc()
1537 return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT)); in getZeroExtendInReg()
1553 return getNode(ISD::SUB, DL, VT, getConstant(0, DL, VT), Val); in getNegative()
1558 return getNode(ISD::XOR, DL, VT, Val, getAllOnesConstant(DL, VT)); in getNOT()
1563 return getNode(ISD::XOR, DL, VT, Val, TrueValue); in getLogicalNOT()
1569 return getNode(ISD::VP_XOR, DL, VT, Val, TrueValue, Mask, EVL); in getVPLogicalNOT()
1580 return getNode(ISD::VP_ZERO_EXTEND, DL, VT, Op, Mask, EVL); in getVPZExtOrTrunc()
1582 return getNode(ISD::VP_TRUNCATE, DL, VT, Op, Mask, EVL); in getVPZExtOrTrunc()
1651 TLI->isOperationLegal(ISD::SPLAT_VECTOR, VT)) { in getConstant()
1662 return getNode(ISD::SPLAT_VECTOR_PARTS, DL, VT, ScalarParts); in getConstant()
1696 getNode(ISD::BITCAST, DL, VT, getBuildVector(ViaVecVT, DL, Ops)); in getConstant()
1702 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; in getConstant()
1757 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; in getConstantFP()
1811 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; in getGlobalAddress()
1813 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; in getGlobalAddress()
1832 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; in getFrameIndex()
1850 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; in getJumpTable()
1868 return getNode(ISD::JUMP_TABLE_DEBUG_INFO, DL, MVT::Glue, Chain, in getJumpTableDebugInfo()
1881 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; in getConstantPool()
1908 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; in getConstantPool()
1928 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), std::nullopt); in getBasicBlock()
1981 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode()
2010 return getNode(ISD::VSCALE, DL, VT, getConstant(MulImm, DL, VT)); in getVScale()
2031 ISD::STEP_VECTOR, DL, ResVT, in getStepVector()
2153 while (V.getOpcode() == ISD::BITCAST) in getVectorShuffle()
2185 NewBV = getNode(ISD::BITCAST, dl, VT, NewBV); in getVectorShuffle()
2193 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); in getVectorShuffle()
2230 AddNodeIDNode(ID, ISD::Register, getVTList(VT), std::nullopt); in getRegister()
2245 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), std::nullopt); in getRegisterMask()
2259 return getLabelNode(ISD::EH_LABEL, dl, Root, Label); in getEHLabel()
2284 unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress; in getBlockAddress()
2303 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), std::nullopt); in getSrcValue()
2318 AddNodeIDNode(ID, ISD::MDNODE_SDNODE, getVTList(MVT::Other), std::nullopt); in getMDNode()
2335 return getNode(ISD::BITCAST, SDLoc(V), VT, V); in getBitcast()
2342 AddNodeIDNode(ID, ISD::ADDRSPACECAST, getVTList(VT), Ops); in getAddrSpaceCast()
2360 return getNode(ISD::FREEZE, SDLoc(V), V.getValueType(), V); in getFreeze()
2387 VAList = getNode(ISD::ADD, dl, VAList.getValueType(), VAList, in expandVAArg()
2391 getNode(ISD::AND, dl, VAList.getValueType(), VAList, in expandVAArg()
2396 Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList, in expandVAArg()
2487 ISD::CondCode Cond, const SDLoc &dl) { in FoldSetCC()
2503 case ISD::SETFALSE: in FoldSetCC()
2504 case ISD::SETFALSE2: return getBoolConstant(false, dl, VT, OpVT); in FoldSetCC()
2505 case ISD::SETTRUE: in FoldSetCC()
2506 case ISD::SETTRUE2: return getBoolConstant(true, dl, VT, OpVT); in FoldSetCC()
2508 case ISD::SETOEQ: in FoldSetCC()
2509 case ISD::SETOGT: in FoldSetCC()
2510 case ISD::SETOGE: in FoldSetCC()
2511 case ISD::SETOLT: in FoldSetCC()
2512 case ISD::SETOLE: in FoldSetCC()
2513 case ISD::SETONE: in FoldSetCC()
2514 case ISD::SETO: in FoldSetCC()
2515 case ISD::SETUO: in FoldSetCC()
2516 case ISD::SETUEQ: in FoldSetCC()
2517 case ISD::SETUNE: in FoldSetCC()
2528 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) in FoldSetCC()
2539 return getBoolConstant(ISD::isTrueWhenEqual(Cond), dl, VT, OpVT); in FoldSetCC()
2559 case ISD::SETEQ: if (R==APFloat::cmpUnordered) in FoldSetCC()
2562 case ISD::SETOEQ: return getBoolConstant(R==APFloat::cmpEqual, dl, VT, in FoldSetCC()
2564 case ISD::SETNE: if (R==APFloat::cmpUnordered) in FoldSetCC()
2567 case ISD::SETONE: return getBoolConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
2570 case ISD::SETLT: if (R==APFloat::cmpUnordered) in FoldSetCC()
2573 case ISD::SETOLT: return getBoolConstant(R==APFloat::cmpLessThan, dl, VT, in FoldSetCC()
2575 case ISD::SETGT: if (R==APFloat::cmpUnordered) in FoldSetCC()
2578 case ISD::SETOGT: return getBoolConstant(R==APFloat::cmpGreaterThan, dl, in FoldSetCC()
2580 case ISD::SETLE: if (R==APFloat::cmpUnordered) in FoldSetCC()
2583 case ISD::SETOLE: return getBoolConstant(R==APFloat::cmpLessThan || in FoldSetCC()
2586 case ISD::SETGE: if (R==APFloat::cmpUnordered) in FoldSetCC()
2589 case ISD::SETOGE: return getBoolConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
2591 case ISD::SETO: return getBoolConstant(R!=APFloat::cmpUnordered, dl, VT, in FoldSetCC()
2593 case ISD::SETUO: return getBoolConstant(R==APFloat::cmpUnordered, dl, VT, in FoldSetCC()
2595 case ISD::SETUEQ: return getBoolConstant(R==APFloat::cmpUnordered || in FoldSetCC()
2598 case ISD::SETUNE: return getBoolConstant(R!=APFloat::cmpEqual, dl, VT, in FoldSetCC()
2600 case ISD::SETULT: return getBoolConstant(R==APFloat::cmpUnordered || in FoldSetCC()
2603 case ISD::SETUGT: return getBoolConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
2606 case ISD::SETULE: return getBoolConstant(R!=APFloat::cmpGreaterThan, dl, in FoldSetCC()
2608 case ISD::SETUGE: return getBoolConstant(R!=APFloat::cmpLessThan, dl, VT, in FoldSetCC()
2613 ISD::CondCode SwappedCond = ISD::getSetCCSwappedOperands(Cond); in FoldSetCC()
2624 switch (ISD::getUnorderedFlavor(Cond)) { in FoldSetCC()
2719 case ISD::SPLAT_VECTOR: in isSplatValue()
2724 case ISD::ADD: in isSplatValue()
2725 case ISD::SUB: in isSplatValue()
2726 case ISD::AND: in isSplatValue()
2727 case ISD::XOR: in isSplatValue()
2728 case ISD::OR: { in isSplatValue()
2739 case ISD::ABS: in isSplatValue()
2740 case ISD::TRUNCATE: in isSplatValue()
2741 case ISD::SIGN_EXTEND: in isSplatValue()
2742 case ISD::ZERO_EXTEND: in isSplatValue()
2745 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN || in isSplatValue()
2746 Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) in isSplatValue()
2762 case ISD::BUILD_VECTOR: { in isSplatValue()
2778 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
2816 case ISD::EXTRACT_SUBVECTOR: { in isSplatValue()
2832 case ISD::ANY_EXTEND_VECTOR_INREG: in isSplatValue()
2833 case ISD::SIGN_EXTEND_VECTOR_INREG: in isSplatValue()
2834 case ISD::ZERO_EXTEND_VECTOR_INREG: { in isSplatValue()
2849 case ISD::BITCAST: { in isSplatValue()
2933 case ISD::SPLAT_VECTOR: in getSplatSourceVector()
2936 case ISD::VECTOR_SHUFFLE: { in getSplatSourceVector()
2966 return getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(V), LegalSVT, SrcVector, in getSplatValue()
2975 assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL || in getValidShiftAmountConstant()
2976 V.getOpcode() == ISD::SRA) && in getValidShiftAmountConstant()
2990 assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL || in getValidMinimumShiftAmountConstant()
2991 V.getOpcode() == ISD::SRA) && in getValidMinimumShiftAmountConstant()
3019 assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL || in getValidMaximumShiftAmountConstant()
3020 V.getOpcode() == ISD::SRA) && in getValidMaximumShiftAmountConstant()
3093 case ISD::MERGE_VALUES: in computeKnownBits()
3096 case ISD::SPLAT_VECTOR: { in computeKnownBits()
3105 case ISD::SPLAT_VECTOR_PARTS: { in computeKnownBits()
3114 case ISD::BUILD_VECTOR: in computeKnownBits()
3140 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
3168 case ISD::VSCALE: { in computeKnownBits()
3174 case ISD::CONCAT_VECTORS: { in computeKnownBits()
3196 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
3222 case ISD::EXTRACT_SUBVECTOR: { in computeKnownBits()
3234 case ISD::SCALAR_TO_VECTOR: { in computeKnownBits()
3249 case ISD::BITCAST: { in computeKnownBits()
3316 case ISD::AND: in computeKnownBits()
3322 case ISD::OR: in computeKnownBits()
3328 case ISD::XOR: in computeKnownBits()
3334 case ISD::MUL: { in computeKnownBits()
3353 case ISD::MULHU: { in computeKnownBits()
3359 case ISD::MULHS: { in computeKnownBits()
3365 case ISD::UMUL_LOHI: { in computeKnownBits()
3376 case ISD::SMUL_LOHI: { in computeKnownBits()
3387 case ISD::AVGCEILU: { in computeKnownBits()
3397 case ISD::SELECT: in computeKnownBits()
3398 case ISD::VSELECT: in computeKnownBits()
3408 case ISD::SELECT_CC: in computeKnownBits()
3418 case ISD::SMULO: in computeKnownBits()
3419 case ISD::UMULO: in computeKnownBits()
3431 case ISD::SETCC: in computeKnownBits()
3432 case ISD::SETCCCARRY: in computeKnownBits()
3433 case ISD::STRICT_FSETCC: in computeKnownBits()
3434 case ISD::STRICT_FSETCCS: { in computeKnownBits()
3443 case ISD::SHL: in computeKnownBits()
3453 case ISD::SRL: in computeKnownBits()
3463 case ISD::SRA: in computeKnownBits()
3468 case ISD::FSHL: in computeKnownBits()
3469 case ISD::FSHR: in computeKnownBits()
3476 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits()
3485 if (Opcode == ISD::FSHL) { in computeKnownBits()
3499 case ISD::SHL_PARTS: in computeKnownBits()
3500 case ISD::SRA_PARTS: in computeKnownBits()
3501 case ISD::SRL_PARTS: { in computeKnownBits()
3514 if (Opcode == ISD::SHL_PARTS) in computeKnownBits()
3516 else if (Opcode == ISD::SRA_PARTS) in computeKnownBits()
3529 case ISD::SIGN_EXTEND_INREG: { in computeKnownBits()
3535 case ISD::CTTZ: in computeKnownBits()
3536 case ISD::CTTZ_ZERO_UNDEF: { in computeKnownBits()
3544 case ISD::CTLZ: in computeKnownBits()
3545 case ISD::CTLZ_ZERO_UNDEF: { in computeKnownBits()
3553 case ISD::CTPOP: { in computeKnownBits()
3560 case ISD::PARITY: { in computeKnownBits()
3565 case ISD::LOAD: { in computeKnownBits()
3568 if (ISD::isNON_EXTLoad(LD) && Cst) { in computeKnownBits()
3616 } else if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { in computeKnownBits()
3625 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { in computeKnownBits()
3645 case ISD::ZERO_EXTEND_VECTOR_INREG: { in computeKnownBits()
3654 case ISD::ZERO_EXTEND: { in computeKnownBits()
3659 case ISD::SIGN_EXTEND_VECTOR_INREG: { in computeKnownBits()
3670 case ISD::SIGN_EXTEND: { in computeKnownBits()
3677 case ISD::ANY_EXTEND_VECTOR_INREG: { in computeKnownBits()
3686 case ISD::ANY_EXTEND: { in computeKnownBits()
3691 case ISD::TRUNCATE: { in computeKnownBits()
3696 case ISD::AssertZext: { in computeKnownBits()
3704 case ISD::AssertAlign: { in computeKnownBits()
3715 case ISD::FGETSIGN: in computeKnownBits()
3719 case ISD::ADD: in computeKnownBits()
3720 case ISD::SUB: { in computeKnownBits()
3724 Known = KnownBits::computeForAddSub(Op.getOpcode() == ISD::ADD, in computeKnownBits()
3728 case ISD::USUBO: in computeKnownBits()
3729 case ISD::SSUBO: in computeKnownBits()
3730 case ISD::USUBO_CARRY: in computeKnownBits()
3731 case ISD::SSUBO_CARRY: in computeKnownBits()
3741 case ISD::SUBC: { in computeKnownBits()
3747 if (Opcode == ISD::USUBO_CARRY || Opcode == ISD::SSUBO_CARRY) { in computeKnownBits()
3760 case ISD::UADDO: in computeKnownBits()
3761 case ISD::SADDO: in computeKnownBits()
3762 case ISD::UADDO_CARRY: in computeKnownBits()
3763 case ISD::SADDO_CARRY: in computeKnownBits()
3773 case ISD::ADDC: in computeKnownBits()
3774 case ISD::ADDE: { in computeKnownBits()
3779 if (Opcode == ISD::ADDE) in computeKnownBits()
3782 else if (Opcode == ISD::UADDO_CARRY || Opcode == ISD::SADDO_CARRY) { in computeKnownBits()
3795 case ISD::UDIV: { in computeKnownBits()
3801 case ISD::SDIV: { in computeKnownBits()
3807 case ISD::SREM: { in computeKnownBits()
3813 case ISD::UREM: { in computeKnownBits()
3819 case ISD::EXTRACT_ELEMENT: { in computeKnownBits()
3832 case ISD::EXTRACT_VECTOR_ELT: { in computeKnownBits()
3860 case ISD::INSERT_VECTOR_ELT: { in computeKnownBits()
3890 case ISD::BITREVERSE: { in computeKnownBits()
3895 case ISD::BSWAP: { in computeKnownBits()
3900 case ISD::ABS: { in computeKnownBits()
3905 case ISD::USUBSAT: { in computeKnownBits()
3911 case ISD::UMIN: { in computeKnownBits()
3917 case ISD::UMAX: { in computeKnownBits()
3923 case ISD::SMIN: in computeKnownBits()
3924 case ISD::SMAX: { in computeKnownBits()
3927 bool IsMax = (Opcode == ISD::SMAX); in computeKnownBits()
3930 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in computeKnownBits()
3975 case ISD::FP_TO_UINT_SAT: { in computeKnownBits()
3981 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: in computeKnownBits()
3994 case ISD::ATOMIC_CMP_SWAP: in computeKnownBits()
3995 case ISD::ATOMIC_SWAP: in computeKnownBits()
3996 case ISD::ATOMIC_LOAD_ADD: in computeKnownBits()
3997 case ISD::ATOMIC_LOAD_SUB: in computeKnownBits()
3998 case ISD::ATOMIC_LOAD_AND: in computeKnownBits()
3999 case ISD::ATOMIC_LOAD_CLR: in computeKnownBits()
4000 case ISD::ATOMIC_LOAD_OR: in computeKnownBits()
4001 case ISD::ATOMIC_LOAD_XOR: in computeKnownBits()
4002 case ISD::ATOMIC_LOAD_NAND: in computeKnownBits()
4003 case ISD::ATOMIC_LOAD_MIN: in computeKnownBits()
4004 case ISD::ATOMIC_LOAD_MAX: in computeKnownBits()
4005 case ISD::ATOMIC_LOAD_UMIN: in computeKnownBits()
4006 case ISD::ATOMIC_LOAD_UMAX: in computeKnownBits()
4007 case ISD::ATOMIC_LOAD: { in computeKnownBits()
4012 if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND) in computeKnownBits()
4017 case ISD::FrameIndex: in computeKnownBits()
4018 case ISD::TargetFrameIndex: in computeKnownBits()
4024 if (Opcode < ISD::BUILTIN_OP_END) in computeKnownBits()
4027 case ISD::INTRINSIC_WO_CHAIN: in computeKnownBits()
4028 case ISD::INTRINSIC_W_CHAIN: in computeKnownBits()
4029 case ISD::INTRINSIC_VOID: in computeKnownBits()
4081 if (N0.getOpcode() == ISD::UMUL_LOHI && N0.getResNo() == 1 && in computeOverflowForUnsignedAdd()
4086 if (N1.getOpcode() == ISD::UMUL_LOHI && N1.getResNo() == 1 && in computeOverflowForUnsignedAdd()
4178 if (ISD::matchUnaryPredicate(Val, [BitWidth](ConstantSDNode *C) { in isKnownToBeAPowerOfTwo()
4185 if (Val.getOpcode() == ISD::SHL) { in isKnownToBeAPowerOfTwo()
4195 if (Val.getOpcode() == ISD::SRL) { in isKnownToBeAPowerOfTwo()
4203 if (Val.getOpcode() == ISD::ROTL || Val.getOpcode() == ISD::ROTR) in isKnownToBeAPowerOfTwo()
4207 if (Val.getOpcode() == ISD::BUILD_VECTOR) in isKnownToBeAPowerOfTwo()
4216 if (Val.getOpcode() == ISD::SPLAT_VECTOR) in isKnownToBeAPowerOfTwo()
4222 if (Val.getOpcode() == ISD::VSCALE && in isKnownToBeAPowerOfTwo()
4227 if (Val.getOpcode() == ISD::SMIN || Val.getOpcode() == ISD::SMAX || in isKnownToBeAPowerOfTwo()
4228 Val.getOpcode() == ISD::UMIN || Val.getOpcode() == ISD::UMAX) in isKnownToBeAPowerOfTwo()
4232 if (Val.getOpcode() == ISD::SELECT || Val.getOpcode() == ISD::VSELECT) in isKnownToBeAPowerOfTwo()
4236 if (Val.getOpcode() == ISD::AND) { in isKnownToBeAPowerOfTwo()
4245 if (NegOp.getOpcode() == ISD::SUB && in isKnownToBeAPowerOfTwo()
4252 if (Val.getOpcode() == ISD::ZERO_EXTEND) in isKnownToBeAPowerOfTwo()
4295 case ISD::AssertSext: in ComputeNumSignBits()
4298 case ISD::AssertZext: in ComputeNumSignBits()
4301 case ISD::MERGE_VALUES: in ComputeNumSignBits()
4304 case ISD::SPLAT_VECTOR: { in ComputeNumSignBits()
4312 case ISD::BUILD_VECTOR: in ComputeNumSignBits()
4339 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
4363 case ISD::BITCAST: { in ComputeNumSignBits()
4409 case ISD::FP_TO_SINT_SAT: in ComputeNumSignBits()
4413 case ISD::SIGN_EXTEND: in ComputeNumSignBits()
4416 case ISD::SIGN_EXTEND_INREG: in ComputeNumSignBits()
4422 case ISD::SIGN_EXTEND_VECTOR_INREG: { in ComputeNumSignBits()
4431 case ISD::SRA: in ComputeNumSignBits()
4438 case ISD::SHL: in ComputeNumSignBits()
4447 case ISD::AND: in ComputeNumSignBits()
4448 case ISD::OR: in ComputeNumSignBits()
4449 case ISD::XOR: // NOT is handled here. in ComputeNumSignBits()
4461 case ISD::SELECT: in ComputeNumSignBits()
4462 case ISD::VSELECT: in ComputeNumSignBits()
4467 case ISD::SELECT_CC: in ComputeNumSignBits()
4473 case ISD::SMIN: in ComputeNumSignBits()
4474 case ISD::SMAX: { in ComputeNumSignBits()
4477 bool IsMax = (Opcode == ISD::SMAX); in ComputeNumSignBits()
4480 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in ComputeNumSignBits()
4500 case ISD::UMIN: in ComputeNumSignBits()
4501 case ISD::UMAX: in ComputeNumSignBits()
4507 case ISD::SADDO: in ComputeNumSignBits()
4508 case ISD::UADDO: in ComputeNumSignBits()
4509 case ISD::SADDO_CARRY: in ComputeNumSignBits()
4510 case ISD::UADDO_CARRY: in ComputeNumSignBits()
4511 case ISD::SSUBO: in ComputeNumSignBits()
4512 case ISD::USUBO: in ComputeNumSignBits()
4513 case ISD::SSUBO_CARRY: in ComputeNumSignBits()
4514 case ISD::USUBO_CARRY: in ComputeNumSignBits()
4515 case ISD::SMULO: in ComputeNumSignBits()
4516 case ISD::UMULO: in ComputeNumSignBits()
4527 case ISD::SETCC: in ComputeNumSignBits()
4528 case ISD::SETCCCARRY: in ComputeNumSignBits()
4529 case ISD::STRICT_FSETCC: in ComputeNumSignBits()
4530 case ISD::STRICT_FSETCCS: { in ComputeNumSignBits()
4538 case ISD::ROTL: in ComputeNumSignBits()
4539 case ISD::ROTR: in ComputeNumSignBits()
4551 if (Opcode == ISD::ROTR) in ComputeNumSignBits()
4559 case ISD::ADD: in ComputeNumSignBits()
4560 case ISD::ADDC: in ComputeNumSignBits()
4587 case ISD::SUB: in ComputeNumSignBits()
4615 case ISD::MUL: { in ComputeNumSignBits()
4627 case ISD::SREM: in ComputeNumSignBits()
4633 case ISD::TRUNCATE: { in ComputeNumSignBits()
4641 case ISD::EXTRACT_ELEMENT: { in ComputeNumSignBits()
4656 case ISD::INSERT_VECTOR_ELT: { in ComputeNumSignBits()
4688 case ISD::EXTRACT_VECTOR_ELT: { in ComputeNumSignBits()
4716 case ISD::EXTRACT_SUBVECTOR: { in ComputeNumSignBits()
4727 case ISD::CONCAT_VECTORS: { in ComputeNumSignBits()
4747 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
4773 case ISD::LOAD: { in ComputeNumSignBits()
4782 case ISD::SEXTLOAD: in ComputeNumSignBits()
4785 case ISD::ZEXTLOAD: in ComputeNumSignBits()
4801 case ISD::ATOMIC_CMP_SWAP: in ComputeNumSignBits()
4802 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: in ComputeNumSignBits()
4803 case ISD::ATOMIC_SWAP: in ComputeNumSignBits()
4804 case ISD::ATOMIC_LOAD_ADD: in ComputeNumSignBits()
4805 case ISD::ATOMIC_LOAD_SUB: in ComputeNumSignBits()
4806 case ISD::ATOMIC_LOAD_AND: in ComputeNumSignBits()
4807 case ISD::ATOMIC_LOAD_CLR: in ComputeNumSignBits()
4808 case ISD::ATOMIC_LOAD_OR: in ComputeNumSignBits()
4809 case ISD::ATOMIC_LOAD_XOR: in ComputeNumSignBits()
4810 case ISD::ATOMIC_LOAD_NAND: in ComputeNumSignBits()
4811 case ISD::ATOMIC_LOAD_MIN: in ComputeNumSignBits()
4812 case ISD::ATOMIC_LOAD_MAX: in ComputeNumSignBits()
4813 case ISD::ATOMIC_LOAD_UMIN: in ComputeNumSignBits()
4814 case ISD::ATOMIC_LOAD_UMAX: in ComputeNumSignBits()
4815 case ISD::ATOMIC_LOAD: { in ComputeNumSignBits()
4821 if (TLI->getExtendForAtomicOps() == ISD::SIGN_EXTEND) in ComputeNumSignBits()
4823 if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND) in ComputeNumSignBits()
4837 case ISD::SEXTLOAD: // e.g. i16->i32 = '17' bits known. in ComputeNumSignBits()
4840 case ISD::ZEXTLOAD: // e.g. i16->i32 = '16' bits known. in ComputeNumSignBits()
4843 case ISD::NON_EXTLOAD: in ComputeNumSignBits()
4879 if (Opcode >= ISD::BUILTIN_OP_END || in ComputeNumSignBits()
4880 Opcode == ISD::INTRINSIC_WO_CHAIN || in ComputeNumSignBits()
4881 Opcode == ISD::INTRINSIC_W_CHAIN || in ComputeNumSignBits()
4882 Opcode == ISD::INTRINSIC_VOID) { in ComputeNumSignBits()
4915 if (Op.getOpcode() == ISD::FREEZE) in isGuaranteedNotToBeUndefOrPoison()
4936 if (Opcode == ISD::FREEZE) in isGuaranteedNotToBeUndefOrPoison()
4946 case ISD::VALUETYPE: in isGuaranteedNotToBeUndefOrPoison()
4947 case ISD::FrameIndex: in isGuaranteedNotToBeUndefOrPoison()
4948 case ISD::TargetFrameIndex: in isGuaranteedNotToBeUndefOrPoison()
4951 case ISD::UNDEF: in isGuaranteedNotToBeUndefOrPoison()
4954 case ISD::BUILD_VECTOR: in isGuaranteedNotToBeUndefOrPoison()
4972 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN || in isGuaranteedNotToBeUndefOrPoison()
4973 Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) in isGuaranteedNotToBeUndefOrPoison()
5015 case ISD::FREEZE: in canCreateUndefOrPoison()
5016 case ISD::CONCAT_VECTORS: in canCreateUndefOrPoison()
5017 case ISD::INSERT_SUBVECTOR: in canCreateUndefOrPoison()
5018 case ISD::AND: in canCreateUndefOrPoison()
5019 case ISD::XOR: in canCreateUndefOrPoison()
5020 case ISD::ROTL: in canCreateUndefOrPoison()
5021 case ISD::ROTR: in canCreateUndefOrPoison()
5022 case ISD::FSHL: in canCreateUndefOrPoison()
5023 case ISD::FSHR: in canCreateUndefOrPoison()
5024 case ISD::BSWAP: in canCreateUndefOrPoison()
5025 case ISD::CTPOP: in canCreateUndefOrPoison()
5026 case ISD::BITREVERSE: in canCreateUndefOrPoison()
5027 case ISD::PARITY: in canCreateUndefOrPoison()
5028 case ISD::SIGN_EXTEND: in canCreateUndefOrPoison()
5029 case ISD::TRUNCATE: in canCreateUndefOrPoison()
5030 case ISD::SIGN_EXTEND_INREG: in canCreateUndefOrPoison()
5031 case ISD::SIGN_EXTEND_VECTOR_INREG: in canCreateUndefOrPoison()
5032 case ISD::ZERO_EXTEND_VECTOR_INREG: in canCreateUndefOrPoison()
5033 case ISD::BITCAST: in canCreateUndefOrPoison()
5034 case ISD::BUILD_VECTOR: in canCreateUndefOrPoison()
5035 case ISD::BUILD_PAIR: in canCreateUndefOrPoison()
5039 case ISD::ZERO_EXTEND: in canCreateUndefOrPoison()
5042 case ISD::ADD: in canCreateUndefOrPoison()
5043 case ISD::SUB: in canCreateUndefOrPoison()
5044 case ISD::MUL: in canCreateUndefOrPoison()
5049 case ISD::SHL: in canCreateUndefOrPoison()
5059 case ISD::OR: in canCreateUndefOrPoison()
5062 case ISD::INSERT_VECTOR_ELT:{ in canCreateUndefOrPoison()
5071 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN || in canCreateUndefOrPoison()
5072 Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) in canCreateUndefOrPoison()
5084 if (Opcode == ISD::OR) in isADDLike()
5087 if (Opcode == ISD::XOR) in isADDLike()
5093 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) || in isBaseWithConstantOffset()
5097 if (Op.getOpcode() == ISD::OR && in isBaseWithConstantOffset()
5120 case ISD::FADD: in isKnownNeverNaN()
5121 case ISD::FSUB: in isKnownNeverNaN()
5122 case ISD::FMUL: in isKnownNeverNaN()
5123 case ISD::FDIV: in isKnownNeverNaN()
5124 case ISD::FREM: in isKnownNeverNaN()
5125 case ISD::FSIN: in isKnownNeverNaN()
5126 case ISD::FCOS: in isKnownNeverNaN()
5127 case ISD::FMA: in isKnownNeverNaN()
5128 case ISD::FMAD: { in isKnownNeverNaN()
5134 case ISD::FCANONICALIZE: in isKnownNeverNaN()
5135 case ISD::FEXP: in isKnownNeverNaN()
5136 case ISD::FEXP2: in isKnownNeverNaN()
5137 case ISD::FEXP10: in isKnownNeverNaN()
5138 case ISD::FTRUNC: in isKnownNeverNaN()
5139 case ISD::FFLOOR: in isKnownNeverNaN()
5140 case ISD::FCEIL: in isKnownNeverNaN()
5141 case ISD::FROUND: in isKnownNeverNaN()
5142 case ISD::FROUNDEVEN: in isKnownNeverNaN()
5143 case ISD::FRINT: in isKnownNeverNaN()
5144 case ISD::LRINT: in isKnownNeverNaN()
5145 case ISD::LLRINT: in isKnownNeverNaN()
5146 case ISD::FNEARBYINT: in isKnownNeverNaN()
5147 case ISD::FLDEXP: { in isKnownNeverNaN()
5152 case ISD::FABS: in isKnownNeverNaN()
5153 case ISD::FNEG: in isKnownNeverNaN()
5154 case ISD::FCOPYSIGN: { in isKnownNeverNaN()
5157 case ISD::SELECT: in isKnownNeverNaN()
5160 case ISD::FP_EXTEND: in isKnownNeverNaN()
5161 case ISD::FP_ROUND: { in isKnownNeverNaN()
5166 case ISD::SINT_TO_FP: in isKnownNeverNaN()
5167 case ISD::UINT_TO_FP: in isKnownNeverNaN()
5169 case ISD::FSQRT: // Need is known positive in isKnownNeverNaN()
5170 case ISD::FLOG: in isKnownNeverNaN()
5171 case ISD::FLOG2: in isKnownNeverNaN()
5172 case ISD::FLOG10: in isKnownNeverNaN()
5173 case ISD::FPOWI: in isKnownNeverNaN()
5174 case ISD::FPOW: { in isKnownNeverNaN()
5180 case ISD::FMINNUM: in isKnownNeverNaN()
5181 case ISD::FMAXNUM: { in isKnownNeverNaN()
5187 case ISD::FMINNUM_IEEE: in isKnownNeverNaN()
5188 case ISD::FMAXNUM_IEEE: { in isKnownNeverNaN()
5198 case ISD::FMINIMUM: in isKnownNeverNaN()
5199 case ISD::FMAXIMUM: { in isKnownNeverNaN()
5204 case ISD::EXTRACT_VECTOR_ELT: { in isKnownNeverNaN()
5207 case ISD::BUILD_VECTOR: { in isKnownNeverNaN()
5214 if (Opcode >= ISD::BUILTIN_OP_END || in isKnownNeverNaN()
5215 Opcode == ISD::INTRINSIC_WO_CHAIN || in isKnownNeverNaN()
5216 Opcode == ISD::INTRINSIC_W_CHAIN || in isKnownNeverNaN()
5217 Opcode == ISD::INTRINSIC_VOID) { in isKnownNeverNaN()
5230 return ISD::matchUnaryFpPredicate( in isKnownNeverZeroFloat()
5242 if (ISD::matchUnaryPredicate(Op, in isKnownNeverZero()
5252 case ISD::OR: in isKnownNeverZero()
5256 case ISD::VSELECT: in isKnownNeverZero()
5257 case ISD::SELECT: in isKnownNeverZero()
5261 case ISD::SHL: { in isKnownNeverZero()
5275 case ISD::UADDSAT: in isKnownNeverZero()
5276 case ISD::UMAX: in isKnownNeverZero()
5282 case ISD::SMAX: in isKnownNeverZero()
5283 case ISD::SMIN: in isKnownNeverZero()
5284 case ISD::UMIN: in isKnownNeverZero()
5288 case ISD::ROTL: in isKnownNeverZero()
5289 case ISD::ROTR: in isKnownNeverZero()
5290 case ISD::BITREVERSE: in isKnownNeverZero()
5291 case ISD::BSWAP: in isKnownNeverZero()
5292 case ISD::CTPOP: in isKnownNeverZero()
5293 case ISD::ABS: in isKnownNeverZero()
5296 case ISD::SRA: in isKnownNeverZero()
5297 case ISD::SRL: { in isKnownNeverZero()
5310 case ISD::UDIV: in isKnownNeverZero()
5311 case ISD::SDIV: in isKnownNeverZero()
5318 case ISD::ADD: in isKnownNeverZero()
5326 case ISD::SUB: { in isKnownNeverZero()
5336 case ISD::MUL: in isKnownNeverZero()
5343 case ISD::ZERO_EXTEND: in isKnownNeverZero()
5344 case ISD::SIGN_EXTEND: in isKnownNeverZero()
5372 if (!MaskC || V.getOpcode() != ISD::ANY_EXTEND) in getBitwiseNotOperand()
5378 ExtArg.getOperand(0).getOpcode() == ISD::TRUNCATE && in getBitwiseNotOperand()
5391 if (NotOperand->getOpcode() == ISD::ZERO_EXTEND || in haveNoCommonBitsSetCommutative()
5392 NotOperand->getOpcode() == ISD::TRUNCATE) in haveNoCommonBitsSetCommutative()
5397 if (Other->getOpcode() == ISD::AND) in haveNoCommonBitsSetCommutative()
5404 if (A->getOpcode() == ISD::ZERO_EXTEND || A->getOpcode() == ISD::TRUNCATE) in haveNoCommonBitsSetCommutative()
5407 if (B->getOpcode() == ISD::ZERO_EXTEND || B->getOpcode() == ISD::TRUNCATE) in haveNoCommonBitsSetCommutative()
5410 if (A->getOpcode() == ISD::AND) in haveNoCommonBitsSetCommutative()
5453 if (Ops[i].getOpcode() != ISD::EXTRACT_VECTOR_ELT || in FoldBUILD_VECTOR()
5499 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR || in foldCONCAT_VECTORS()
5529 else if (Op.getOpcode() == ISD::BUILD_VECTOR) in foldCONCAT_VECTORS()
5584 assert(N1.getOpcode() != ISD::DELETED_NODE && "Operand is DELETED_NODE!"); in getNode()
5592 case ISD::FNEG: in getNode()
5593 case ISD::FABS: in getNode()
5594 case ISD::FCEIL: in getNode()
5595 case ISD::FTRUNC: in getNode()
5596 case ISD::FFLOOR: in getNode()
5597 case ISD::FP_EXTEND: in getNode()
5598 case ISD::FP_TO_SINT: in getNode()
5599 case ISD::FP_TO_UINT: in getNode()
5600 case ISD::FP_TO_FP16: in getNode()
5601 case ISD::FP_TO_BF16: in getNode()
5602 case ISD::TRUNCATE: in getNode()
5603 case ISD::ANY_EXTEND: in getNode()
5604 case ISD::ZERO_EXTEND: in getNode()
5605 case ISD::SIGN_EXTEND: in getNode()
5606 case ISD::UINT_TO_FP: in getNode()
5607 case ISD::SINT_TO_FP: in getNode()
5608 case ISD::FP16_TO_FP: in getNode()
5609 case ISD::BF16_TO_FP: in getNode()
5610 case ISD::BITCAST: in getNode()
5611 case ISD::ABS: in getNode()
5612 case ISD::BITREVERSE: in getNode()
5613 case ISD::BSWAP: in getNode()
5614 case ISD::CTLZ: in getNode()
5615 case ISD::CTLZ_ZERO_UNDEF: in getNode()
5616 case ISD::CTTZ: in getNode()
5617 case ISD::CTTZ_ZERO_UNDEF: in getNode()
5618 case ISD::CTPOP: in getNode()
5619 case ISD::STEP_VECTOR: { in getNode()
5628 case ISD::STEP_VECTOR: in getNode()
5631 assert(OpOpcode == ISD::TargetConstant && in getNode()
5635 case ISD::FREEZE: in getNode()
5641 case ISD::TokenFactor: in getNode()
5642 case ISD::MERGE_VALUES: in getNode()
5643 case ISD::CONCAT_VECTORS: in getNode()
5645 case ISD::BUILD_VECTOR: { in getNode()
5652 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
5653 case ISD::FP_EXTEND: in getNode()
5664 case ISD::FP_TO_SINT: in getNode()
5665 case ISD::FP_TO_UINT: in getNode()
5669 case ISD::SINT_TO_FP: in getNode()
5670 case ISD::UINT_TO_FP: in getNode()
5675 case ISD::SIGN_EXTEND: in getNode()
5686 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) in getNode()
5688 if (OpOpcode == ISD::UNDEF) in getNode()
5692 case ISD::ZERO_EXTEND: in getNode()
5703 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) in getNode()
5704 return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0)); in getNode()
5705 if (OpOpcode == ISD::UNDEF) in getNode()
5713 if (OpOpcode == ISD::TRUNCATE) { in getNode()
5716 if (OpOp.getOpcode() != ISD::AND) { in getNode()
5727 case ISD::ANY_EXTEND: in getNode()
5739 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
5740 OpOpcode == ISD::ANY_EXTEND) in getNode()
5743 if (OpOpcode == ISD::UNDEF) in getNode()
5747 if (OpOpcode == ISD::TRUNCATE) { in getNode()
5755 case ISD::TRUNCATE: in getNode()
5766 if (OpOpcode == ISD::TRUNCATE) in getNode()
5767 return getNode(ISD::TRUNCATE, DL, VT, N1.getOperand(0)); in getNode()
5768 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
5769 OpOpcode == ISD::ANY_EXTEND) { in getNode()
5775 return getNode(ISD::TRUNCATE, DL, VT, N1.getOperand(0)); in getNode()
5778 if (OpOpcode == ISD::UNDEF) in getNode()
5780 if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes) in getNode()
5784 case ISD::ANY_EXTEND_VECTOR_INREG: in getNode()
5785 case ISD::ZERO_EXTEND_VECTOR_INREG: in getNode()
5786 case ISD::SIGN_EXTEND_VECTOR_INREG: in getNode()
5794 case ISD::ABS: in getNode()
5796 if (OpOpcode == ISD::UNDEF) in getNode()
5799 case ISD::BSWAP: in getNode()
5803 if (OpOpcode == ISD::UNDEF) in getNode()
5806 if (OpOpcode == ISD::BSWAP) in getNode()
5809 case ISD::BITREVERSE: in getNode()
5811 if (OpOpcode == ISD::UNDEF) in getNode()
5814 case ISD::BITCAST: in getNode()
5818 if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x) in getNode()
5819 return getNode(ISD::BITCAST, DL, VT, N1.getOperand(0)); in getNode()
5820 if (OpOpcode == ISD::UNDEF) in getNode()
5823 case ISD::SCALAR_TO_VECTOR: in getNode()
5830 if (OpOpcode == ISD::UNDEF) in getNode()
5833 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && in getNode()
5839 case ISD::FNEG: in getNode()
5841 if (OpOpcode == ISD::UNDEF) in getNode()
5844 if (OpOpcode == ISD::FNEG) // --X -> X in getNode()
5847 case ISD::FABS: in getNode()
5848 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) in getNode()
5849 return getNode(ISD::FABS, DL, VT, N1.getOperand(0)); in getNode()
5851 case ISD::VSCALE: in getNode()
5854 case ISD::CTPOP: in getNode()
5858 case ISD::CTLZ: in getNode()
5859 case ISD::CTTZ: in getNode()
5863 case ISD::VECREDUCE_ADD: in getNode()
5865 return getNode(ISD::VECREDUCE_XOR, DL, VT, N1); in getNode()
5867 case ISD::VECREDUCE_SMIN: in getNode()
5868 case ISD::VECREDUCE_UMAX: in getNode()
5870 return getNode(ISD::VECREDUCE_OR, DL, VT, N1); in getNode()
5872 case ISD::VECREDUCE_SMAX: in getNode()
5873 case ISD::VECREDUCE_UMIN: in getNode()
5875 return getNode(ISD::VECREDUCE_AND, DL, VT, N1); in getNode()
5909 case ISD::ADD: return C1 + C2; in FoldValue()
5910 case ISD::SUB: return C1 - C2; in FoldValue()
5911 case ISD::MUL: return C1 * C2; in FoldValue()
5912 case ISD::AND: return C1 & C2; in FoldValue()
5913 case ISD::OR: return C1 | C2; in FoldValue()
5914 case ISD::XOR: return C1 ^ C2; in FoldValue()
5915 case ISD::SHL: return C1 << C2; in FoldValue()
5916 case ISD::SRL: return C1.lshr(C2); in FoldValue()
5917 case ISD::SRA: return C1.ashr(C2); in FoldValue()
5918 case ISD::ROTL: return C1.rotl(C2); in FoldValue()
5919 case ISD::ROTR: return C1.rotr(C2); in FoldValue()
5920 case ISD::SMIN: return C1.sle(C2) ? C1 : C2; in FoldValue()
5921 case ISD::SMAX: return C1.sge(C2) ? C1 : C2; in FoldValue()
5922 case ISD::UMIN: return C1.ule(C2) ? C1 : C2; in FoldValue()
5923 case ISD::UMAX: return C1.uge(C2) ? C1 : C2; in FoldValue()
5924 case ISD::SADDSAT: return C1.sadd_sat(C2); in FoldValue()
5925 case ISD::UADDSAT: return C1.uadd_sat(C2); in FoldValue()
5926 case ISD::SSUBSAT: return C1.ssub_sat(C2); in FoldValue()
5927 case ISD::USUBSAT: return C1.usub_sat(C2); in FoldValue()
5928 case ISD::SSHLSAT: return C1.sshl_sat(C2); in FoldValue()
5929 case ISD::USHLSAT: return C1.ushl_sat(C2); in FoldValue()
5930 case ISD::UDIV: in FoldValue()
5934 case ISD::UREM: in FoldValue()
5938 case ISD::SDIV: in FoldValue()
5942 case ISD::SREM: in FoldValue()
5946 case ISD::MULHS: { in FoldValue()
5952 case ISD::MULHU: { in FoldValue()
5958 case ISD::AVGFLOORS: { in FoldValue()
5964 case ISD::AVGFLOORU: { in FoldValue()
5970 case ISD::AVGCEILS: { in FoldValue()
5976 case ISD::AVGCEILU: { in FoldValue()
5982 case ISD::ABDS: in FoldValue()
5984 case ISD::ABDU: in FoldValue()
6000 if (Opcode == ISD::AND || Opcode == ISD::MUL) in FoldValueWithUndef()
6009 if (GA->getOpcode() != ISD::GlobalAddress) in FoldSymbolOffset()
6018 case ISD::ADD: break; in FoldSymbolOffset()
6019 case ISD::SUB: Offset = -uint64_t(Offset); break; in FoldSymbolOffset()
6028 case ISD::SDIV: in isUndef()
6029 case ISD::UDIV: in isUndef()
6030 case ISD::SREM: in isUndef()
6031 case ISD::UREM: { in isUndef()
6039 return ISD::isBuildVectorOfConstantSDNodes(Divisor.getNode()) && in isUndef()
6059 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::CONCAT_VECTORS) in FoldConstantArithmetic()
6081 case ISD::SIGN_EXTEND: in FoldConstantArithmetic()
6084 case ISD::TRUNCATE: in FoldConstantArithmetic()
6088 case ISD::ZERO_EXTEND: in FoldConstantArithmetic()
6091 case ISD::ANY_EXTEND: in FoldConstantArithmetic()
6098 case ISD::ABS: in FoldConstantArithmetic()
6101 case ISD::BITREVERSE: in FoldConstantArithmetic()
6104 case ISD::BSWAP: in FoldConstantArithmetic()
6107 case ISD::CTPOP: in FoldConstantArithmetic()
6110 case ISD::CTLZ: in FoldConstantArithmetic()
6111 case ISD::CTLZ_ZERO_UNDEF: in FoldConstantArithmetic()
6114 case ISD::CTTZ: in FoldConstantArithmetic()
6115 case ISD::CTTZ_ZERO_UNDEF: in FoldConstantArithmetic()
6118 case ISD::UINT_TO_FP: in FoldConstantArithmetic()
6119 case ISD::SINT_TO_FP: { in FoldConstantArithmetic()
6122 (void)apf.convertFromAPInt(Val, Opcode == ISD::SINT_TO_FP, in FoldConstantArithmetic()
6126 case ISD::FP16_TO_FP: in FoldConstantArithmetic()
6127 case ISD::BF16_TO_FP: { in FoldConstantArithmetic()
6129 APFloat FPV(Opcode == ISD::FP16_TO_FP ? APFloat::IEEEhalf() in FoldConstantArithmetic()
6139 case ISD::STEP_VECTOR: in FoldConstantArithmetic()
6143 case ISD::BITCAST: in FoldConstantArithmetic()
6160 case ISD::FNEG: in FoldConstantArithmetic()
6163 case ISD::FABS: in FoldConstantArithmetic()
6166 case ISD::FCEIL: { in FoldConstantArithmetic()
6172 case ISD::FTRUNC: { in FoldConstantArithmetic()
6178 case ISD::FFLOOR: { in FoldConstantArithmetic()
6184 case ISD::FP_EXTEND: { in FoldConstantArithmetic()
6192 case ISD::FP_TO_SINT: in FoldConstantArithmetic()
6193 case ISD::FP_TO_UINT: { in FoldConstantArithmetic()
6195 APSInt IntVal(VT.getSizeInBits(), Opcode == ISD::FP_TO_UINT); in FoldConstantArithmetic()
6203 case ISD::FP_TO_FP16: in FoldConstantArithmetic()
6204 case ISD::FP_TO_BF16: { in FoldConstantArithmetic()
6208 (void)V.convert(Opcode == ISD::FP_TO_FP16 ? APFloat::IEEEhalf() in FoldConstantArithmetic()
6213 case ISD::BITCAST: in FoldConstantArithmetic()
6230 if (Opcode == ISD::BITCAST) in FoldConstantArithmetic()
6273 Ops[0].getOpcode() == ISD::BITCAST && in FoldConstantArithmetic()
6274 Ops[1].getOpcode() == ISD::BITCAST) { in FoldConstantArithmetic()
6319 if ((Opcode == ISD::MUL || Opcode == ISD::SHL) && in FoldConstantArithmetic()
6320 Ops[0].getOpcode() == ISD::STEP_VECTOR) { in FoldConstantArithmetic()
6322 if (ISD::isConstantSplatVector(Ops[1].getNode(), RHSVal)) { in FoldConstantArithmetic()
6323 APInt NewStep = Opcode == ISD::MUL in FoldConstantArithmetic()
6336 return Op.isUndef() || Op.getOpcode() == ISD::CONDCODE || in FoldConstantArithmetic()
6337 Op.getOpcode() == ISD::BUILD_VECTOR || in FoldConstantArithmetic()
6338 Op.getOpcode() == ISD::SPLAT_VECTOR; in FoldConstantArithmetic()
6351 EVT SVT = (Opcode == ISD::SETCC ? MVT::i1 : VT.getScalarType()); in FoldConstantArithmetic()
6352 ISD::NodeType ExtendCode = in FoldConstantArithmetic()
6353 (Opcode == ISD::SETCC && SVT != VT.getScalarType()) in FoldConstantArithmetic()
6355 : ISD::SIGN_EXTEND; in FoldConstantArithmetic()
6377 if (Op.getOpcode() != ISD::BUILD_VECTOR && in FoldConstantArithmetic()
6378 Op.getOpcode() != ISD::SPLAT_VECTOR) { in FoldConstantArithmetic()
6387 Op.getOperand(Op.getOpcode() == ISD::SPLAT_VECTOR ? 0 : I); in FoldConstantArithmetic()
6402 ScalarOp = getNode(ISD::TRUNCATE, DL, InSVT, ScalarOp); in FoldConstantArithmetic()
6416 if (!ScalarResult.isUndef() && ScalarResult.getOpcode() != ISD::Constant && in FoldConstantArithmetic()
6417 ScalarResult.getOpcode() != ISD::ConstantFP) in FoldConstantArithmetic()
6446 case ISD::FADD: in foldConstantFPMath()
6449 case ISD::FSUB: in foldConstantFPMath()
6452 case ISD::FMUL: in foldConstantFPMath()
6455 case ISD::FDIV: in foldConstantFPMath()
6458 case ISD::FREM: in foldConstantFPMath()
6461 case ISD::FCOPYSIGN: in foldConstantFPMath()
6464 case ISD::FMINNUM: in foldConstantFPMath()
6466 case ISD::FMAXNUM: in foldConstantFPMath()
6468 case ISD::FMINIMUM: in foldConstantFPMath()
6470 case ISD::FMAXIMUM: in foldConstantFPMath()
6475 if (N1CFP && Opcode == ISD::FP_ROUND) { in foldConstantFPMath()
6486 case ISD::FSUB: in foldConstantFPMath()
6493 case ISD::FADD: in foldConstantFPMath()
6494 case ISD::FMUL: in foldConstantFPMath()
6495 case ISD::FDIV: in foldConstantFPMath()
6496 case ISD::FREM: in foldConstantFPMath()
6516 AddNodeIDNode(ID, ISD::AssertAlign, getVTList(Val.getValueType()), {Val}); in getAssertAlign()
6559 else if (N1.getOpcode() == ISD::SPLAT_VECTOR && in canonicalizeCommutativeBinop()
6560 N2.getOpcode() == ISD::STEP_VECTOR) in canonicalizeCommutativeBinop()
6566 assert(N1.getOpcode() != ISD::DELETED_NODE && in getNode()
6567 N2.getOpcode() != ISD::DELETED_NODE && in getNode()
6582 case ISD::TokenFactor: in getNode()
6586 if (N1.getOpcode() == ISD::EntryToken) return N2; in getNode()
6587 if (N2.getOpcode() == ISD::EntryToken) return N1; in getNode()
6590 case ISD::BUILD_VECTOR: { in getNode()
6597 case ISD::CONCAT_VECTORS: { in getNode()
6603 case ISD::AND: in getNode()
6614 case ISD::OR: in getNode()
6615 case ISD::XOR: in getNode()
6616 case ISD::ADD: in getNode()
6617 case ISD::SUB: in getNode()
6625 if ((Opcode == ISD::ADD || Opcode == ISD::SUB) && VT.isVector() && in getNode()
6627 return getNode(ISD::XOR, DL, VT, N1, N2); in getNode()
6629 case ISD::MUL: in getNode()
6634 return getNode(ISD::AND, DL, VT, N1, N2); in getNode()
6635 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
6641 case ISD::UDIV: in getNode()
6642 case ISD::UREM: in getNode()
6643 case ISD::MULHU: in getNode()
6644 case ISD::MULHS: in getNode()
6645 case ISD::SDIV: in getNode()
6646 case ISD::SREM: in getNode()
6647 case ISD::SADDSAT: in getNode()
6648 case ISD::SSUBSAT: in getNode()
6649 case ISD::UADDSAT: in getNode()
6650 case ISD::USUBSAT: in getNode()
6656 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) in getNode()
6657 return getNode(ISD::OR, DL, VT, N1, N2); in getNode()
6659 if (Opcode == ISD::SSUBSAT || Opcode == ISD::USUBSAT) in getNode()
6660 return getNode(ISD::AND, DL, VT, N1, getNOT(DL, N2, VT)); in getNode()
6663 case ISD::ABDS: in getNode()
6664 case ISD::ABDU: in getNode()
6669 case ISD::SMIN: in getNode()
6670 case ISD::UMAX: in getNode()
6675 return getNode(ISD::OR, DL, VT, N1, N2); in getNode()
6677 case ISD::SMAX: in getNode()
6678 case ISD::UMIN: in getNode()
6683 return getNode(ISD::AND, DL, VT, N1, N2); in getNode()
6685 case ISD::FADD: in getNode()
6686 case ISD::FSUB: in getNode()
6687 case ISD::FMUL: in getNode()
6688 case ISD::FDIV: in getNode()
6689 case ISD::FREM: in getNode()
6696 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. in getNode()
6702 case ISD::SHL: in getNode()
6703 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
6709 case ISD::SRA: in getNode()
6710 case ISD::SRL: in getNode()
6714 case ISD::ROTL: in getNode()
6715 case ISD::ROTR: in getNode()
6738 case ISD::FP_ROUND: in getNode()
6746 case ISD::AssertSext: in getNode()
6747 case ISD::AssertZext: { in getNode()
6759 case ISD::SIGN_EXTEND_INREG: { in getNode()
6785 if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) { in getNode()
6801 if (N1.getOpcode() == ISD::SPLAT_VECTOR && in getNode()
6804 ISD::SPLAT_VECTOR, DL, VT, in getNode()
6809 case ISD::FP_TO_SINT_SAT: in getNode()
6810 case ISD::FP_TO_UINT_SAT: { in getNode()
6825 case ISD::EXTRACT_VECTOR_ELT: in getNode()
6845 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
6849 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in getNode()
6856 if (N2C && (N1.getOpcode() == ISD::BUILD_VECTOR || in getNode()
6857 N1.getOpcode() == ISD::SPLAT_VECTOR)) { in getNode()
6858 assert((N1.getOpcode() != ISD::BUILD_VECTOR || in getNode()
6862 N1.getOpcode() == ISD::BUILD_VECTOR ? N2C->getZExtValue() : 0; in getNode()
6876 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { in getNode()
6893 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); in getNode()
6905 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
6908 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), in getNode()
6912 case ISD::EXTRACT_ELEMENT: in getNode()
6922 if (N1.getOpcode() == ISD::BUILD_PAIR) in getNode()
6933 case ISD::EXTRACT_SUBVECTOR: { in getNode()
6963 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
6971 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
6988 case ISD::SUB: in getNode()
6990 case ISD::SIGN_EXTEND_INREG: in getNode()
6991 case ISD::UDIV: in getNode()
6992 case ISD::SDIV: in getNode()
6993 case ISD::UREM: in getNode()
6994 case ISD::SREM: in getNode()
6995 case ISD::SSUBSAT: in getNode()
6996 case ISD::USUBSAT: in getNode()
7005 case ISD::XOR: in getNode()
7011 case ISD::ADD: in getNode()
7012 case ISD::SUB: in getNode()
7013 case ISD::UDIV: in getNode()
7014 case ISD::SDIV: in getNode()
7015 case ISD::UREM: in getNode()
7016 case ISD::SREM: in getNode()
7018 case ISD::MUL: in getNode()
7019 case ISD::AND: in getNode()
7020 case ISD::SSUBSAT: in getNode()
7021 case ISD::USUBSAT: in getNode()
7023 case ISD::OR: in getNode()
7024 case ISD::SADDSAT: in getNode()
7025 case ISD::UADDSAT: in getNode()
7069 assert(N1.getOpcode() != ISD::DELETED_NODE && in getNode()
7070 N2.getOpcode() != ISD::DELETED_NODE && in getNode()
7071 N3.getOpcode() != ISD::DELETED_NODE && in getNode()
7075 case ISD::FMA: in getNode()
7076 case ISD::FMAD: { in getNode()
7087 if (Opcode == ISD::FMAD) { in getNode()
7096 case ISD::BUILD_VECTOR: { in getNode()
7103 case ISD::CONCAT_VECTORS: { in getNode()
7109 case ISD::SETCC: { in getNode()
7129 case ISD::SELECT: in getNode()
7130 case ISD::VSELECT: in getNode()
7134 case ISD::VECTOR_SHUFFLE: in getNode()
7136 case ISD::VECTOR_SPLICE: { in getNode()
7141 case ISD::INSERT_VECTOR_ELT: { in getNode()
7160 case ISD::INSERT_SUBVECTOR: { in getNode()
7193 if (N1.isUndef() && N2.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
7198 case ISD::BITCAST: in getNode()
7203 case ISD::VP_TRUNCATE: in getNode()
7204 case ISD::VP_SIGN_EXTEND: in getNode()
7205 case ISD::VP_ZERO_EXTEND: in getNode()
7271 return getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in getStackArgumentTokenFactor()
7298 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
7303 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
7330 return DAG.getNode(ISD::BITCAST, dl, VT, in getMemsetStringVal()
7381 return getNode(ISD::ADD, DL, BasePtrVT, Ptr, Offset, Flags); in getMemBasePlusOffset()
7388 if (Src.getOpcode() == ISD::GlobalAddress) in isMemSrcFromConstant()
7390 else if (Src.getOpcode() == ISD::ADD && in isMemSrcFromConstant()
7391 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && in isMemSrcFromConstant()
7392 Src.getOperand(1).getOpcode() == ISD::Constant) { in isMemSrcFromConstant()
7425 SDValue LoadToken = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in chainLoadsAndStoresForMemcpy()
7577 ISD::EXTLOAD, dl, NVT, Chain, in getMemcpyLoadsAndStores()
7637 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in getMemcpyLoadsAndStores()
7728 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in getMemmoveLoadsAndStores()
7743 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in getMemmoveLoadsAndStores()
7851 Value = DAG.getNode(ISD::TRUNCATE, dl, VT, MemSetValue); in getMemsetStores()
7860 SDValue TailValue = DAG.getNode(ISD::BITCAST, dl, SVT, MemSetValue); in getMemsetStores()
7861 Value = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, TailValue, in getMemsetStores()
7878 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in getMemsetStores()
8262 assert(Opcode == ISD::ATOMIC_CMP_SWAP || in getAtomicCmpSwap()
8263 Opcode == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS); in getAtomicCmpSwap()
8273 assert((Opcode == ISD::ATOMIC_LOAD_ADD || in getAtomic()
8274 Opcode == ISD::ATOMIC_LOAD_SUB || in getAtomic()
8275 Opcode == ISD::ATOMIC_LOAD_AND || in getAtomic()
8276 Opcode == ISD::ATOMIC_LOAD_CLR || in getAtomic()
8277 Opcode == ISD::ATOMIC_LOAD_OR || in getAtomic()
8278 Opcode == ISD::ATOMIC_LOAD_XOR || in getAtomic()
8279 Opcode == ISD::ATOMIC_LOAD_NAND || in getAtomic()
8280 Opcode == ISD::ATOMIC_LOAD_MIN || in getAtomic()
8281 Opcode == ISD::ATOMIC_LOAD_MAX || in getAtomic()
8282 Opcode == ISD::ATOMIC_LOAD_UMIN || in getAtomic()
8283 Opcode == ISD::ATOMIC_LOAD_UMAX || in getAtomic()
8284 Opcode == ISD::ATOMIC_LOAD_FADD || in getAtomic()
8285 Opcode == ISD::ATOMIC_LOAD_FSUB || in getAtomic()
8286 Opcode == ISD::ATOMIC_LOAD_FMAX || in getAtomic()
8287 Opcode == ISD::ATOMIC_LOAD_FMIN || in getAtomic()
8288 Opcode == ISD::ATOMIC_LOAD_UINC_WRAP || in getAtomic()
8289 Opcode == ISD::ATOMIC_LOAD_UDEC_WRAP || in getAtomic()
8290 Opcode == ISD::ATOMIC_SWAP || in getAtomic()
8291 Opcode == ISD::ATOMIC_STORE) && in getAtomic()
8296 SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) : in getAtomic()
8305 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op"); in getAtomic()
8321 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops); in getMergeValues()
8344 assert((Opcode == ISD::INTRINSIC_VOID || in getMemIntrinsicNode()
8345 Opcode == ISD::INTRINSIC_W_CHAIN || in getMemIntrinsicNode()
8346 Opcode == ISD::PREFETCH || in getMemIntrinsicNode()
8348 (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) && in getMemIntrinsicNode()
8386 const unsigned Opcode = IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END; in getLifetimeNode()
8416 const unsigned Opcode = ISD::PSEUDO_PROBE; in getPseudoProbeNode()
8450 if (Ptr.getOpcode() != ISD::ADD || in InferPointerInfo()
8476 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
8500 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
8505 ExtType = ISD::NON_EXTLOAD; in getLoad()
8506 } else if (ExtType == ISD::NON_EXTLOAD) { in getLoad()
8521 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
8528 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops); in getLoad()
8556 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
8563 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
8567 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, in getExtLoad()
8574 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, PtrInfo, in getExtLoad()
8578 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, in getExtLoad()
8582 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
8588 ISD::MemIndexedMode AM) { in getIndexedLoad()
8630 AddNodeIDNode(ID, ISD::STORE, VTs, Ops); in getStore()
8633 dl.getIROrder(), VTs, ISD::UNINDEXED, false, VT, MMO)); in getStore()
8642 ISD::UNINDEXED, false, VT, MMO); in getStore()
8697 AddNodeIDNode(ID, ISD::STORE, VTs, Ops); in getTruncStore()
8700 dl.getIROrder(), VTs, ISD::UNINDEXED, true, SVT, MMO)); in getTruncStore()
8709 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
8721 ISD::MemIndexedMode AM) { in getIndexedStore()
8727 AddNodeIDNode(ID, ISD::STORE, VTs, Ops); in getIndexedStore()
8749 ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, in getLoadVP()
8771 SDValue SelectionDAG::getLoadVP(ISD::MemIndexedMode AM, in getLoadVP()
8772 ISD::LoadExtType ExtType, EVT VT, in getLoadVP()
8777 bool Indexed = AM != ISD::UNINDEXED; in getLoadVP()
8784 AddNodeIDNode(ID, ISD::VP_LOAD, VTs, Ops); in getLoadVP()
8814 return getLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoadVP()
8823 return getLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoadVP()
8827 SDValue SelectionDAG::getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl, in getExtLoadVP()
8835 return getLoadVP(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, Mask, in getExtLoadVP()
8840 SDValue SelectionDAG::getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl, in getExtLoadVP()
8845 return getLoadVP(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, Mask, in getExtLoadVP()
8851 ISD::MemIndexedMode AM) { in getIndexedLoadVP()
8868 ISD::MemIndexedMode AM, bool IsTruncating, in getStoreVP()
8871 bool Indexed = AM != ISD::UNINDEXED; in getStoreVP()
8877 AddNodeIDNode(ID, ISD::VP_STORE, VTs, Ops); in getStoreVP()
8932 EVL, VT, MMO, ISD::UNINDEXED, in getTruncStoreVP()
8948 AddNodeIDNode(ID, ISD::VP_STORE, VTs, Ops); in getTruncStoreVP()
8951 dl.getIROrder(), VTs, ISD::UNINDEXED, true, IsCompressing, SVT, MMO)); in getTruncStoreVP()
8961 ISD::UNINDEXED, true, IsCompressing, SVT, MMO); in getTruncStoreVP()
8973 ISD::MemIndexedMode AM) { in getIndexedStoreVP()
8980 AddNodeIDNode(ID, ISD::VP_STORE, VTs, Ops); in getIndexedStoreVP()
9002 ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, in getStridedLoadVP()
9025 ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, in getStridedLoadVP()
9028 bool Indexed = AM != ISD::UNINDEXED; in getStridedLoadVP()
9035 AddNodeIDNode(ID, ISD::EXPERIMENTAL_VP_STRIDED_LOAD, VTs, Ops); in getStridedLoadVP()
9064 return getStridedLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, DL, Chain, Ptr, in getStridedLoadVP()
9075 return getStridedLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, DL, Chain, Ptr, in getStridedLoadVP()
9080 ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, in getExtStridedLoadVP()
9086 return getStridedLoadVP(ISD::UNINDEXED, ExtType, VT, DL, Chain, Ptr, Undef, in getExtStridedLoadVP()
9092 ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, in getExtStridedLoadVP()
9096 return getStridedLoadVP(ISD::UNINDEXED, ExtType, VT, DL, Chain, Ptr, Undef, in getExtStridedLoadVP()
9102 ISD::MemIndexedMode AM) { in getIndexedStridedLoadVP()
9122 ISD::MemIndexedMode AM, in getStridedStoreVP()
9125 bool Indexed = AM != ISD::UNINDEXED; in getStridedStoreVP()
9131 AddNodeIDNode(ID, ISD::EXPERIMENTAL_VP_STRIDED_STORE, VTs, Ops); in getStridedStoreVP()
9184 Stride, Mask, EVL, VT, MMO, ISD::UNINDEXED, in getTruncStridedStoreVP()
9200 AddNodeIDNode(ID, ISD::EXPERIMENTAL_VP_STRIDED_STORE, VTs, Ops); in getTruncStridedStoreVP()
9203 DL.getIROrder(), VTs, ISD::UNINDEXED, true, IsCompressing, SVT, MMO)); in getTruncStridedStoreVP()
9211 VTs, ISD::UNINDEXED, true, in getTruncStridedStoreVP()
9225 ISD::MemIndexedMode AM) { in getIndexedStridedStoreVP()
9234 AddNodeIDNode(ID, ISD::EXPERIMENTAL_VP_STRIDED_STORE, VTs, Ops); in getIndexedStridedStoreVP()
9256 ISD::MemIndexType IndexType) { in getGatherVP()
9260 AddNodeIDNode(ID, ISD::VP_GATHER, VTs, Ops); in getGatherVP()
9300 ISD::MemIndexType IndexType) { in getScatterVP()
9304 AddNodeIDNode(ID, ISD::VP_SCATTER, VTs, Ops); in getScatterVP()
9345 ISD::MemIndexedMode AM, in getMaskedLoad()
9346 ISD::LoadExtType ExtTy, bool isExpanding) { in getMaskedLoad()
9347 bool Indexed = AM != ISD::UNINDEXED; in getMaskedLoad()
9354 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
9378 ISD::MemIndexedMode AM) { in getIndexedMaskedLoad()
9391 ISD::MemIndexedMode AM, bool IsTruncating, in getMaskedStore()
9395 bool Indexed = AM != ISD::UNINDEXED; in getMaskedStore()
9402 AddNodeIDNode(ID, ISD::MSTORE, VTs, Ops); in getMaskedStore()
9427 ISD::MemIndexedMode AM) { in getIndexedMaskedStore()
9439 ISD::MemIndexType IndexType, in getMaskedGather()
9440 ISD::LoadExtType ExtTy) { in getMaskedGather()
9444 AddNodeIDNode(ID, ISD::MGATHER, VTs, Ops); in getMaskedGather()
9486 ISD::MemIndexType IndexType, in getMaskedScatter()
9491 AddNodeIDNode(ID, ISD::MSCATTER, VTs, Ops); in getMaskedScatter()
9535 AddNodeIDNode(ID, ISD::GET_FPENV_MEM, VTs, Ops); in getGetFPEnv()
9538 ISD::GET_FPENV_MEM, dl.getIROrder(), VTs, MemVT, MMO)); in getGetFPEnv()
9545 auto *N = newSDNode<FPStateAccessSDNode>(ISD::GET_FPENV_MEM, dl.getIROrder(), in getGetFPEnv()
9562 AddNodeIDNode(ID, ISD::SET_FPENV_MEM, VTs, Ops); in getSetFPEnv()
9565 ISD::SET_FPENV_MEM, dl.getIROrder(), VTs, MemVT, MMO)); in getSetFPEnv()
9572 auto *N = newSDNode<FPStateAccessSDNode>(ISD::SET_FPENV_MEM, dl.getIROrder(), in getSetFPEnv()
9631 if (ISD::matchUnaryPredicate(Y, isShiftTooBig, true)) in simplifyShift()
9659 if (Opcode == ISD::FADD) in simplifyFPBinop()
9664 if (Opcode == ISD::FSUB) in simplifyFPBinop()
9670 if (Opcode == ISD::FMUL || Opcode == ISD::FDIV) in simplifyFPBinop()
9675 if (Opcode == ISD::FMUL && Flags.hasNoNaNs() && Flags.hasNoSignedZeros()) in simplifyFPBinop()
9685 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops); in getVAArg()
9725 assert(Op.getOpcode() != ISD::DELETED_NODE && in getNode()
9731 case ISD::BUILD_VECTOR: in getNode()
9736 case ISD::CONCAT_VECTORS: in getNode()
9740 case ISD::SELECT_CC: in getNode()
9754 case ISD::BR_CC: in getNode()
9759 case ISD::VP_ADD: in getNode()
9760 case ISD::VP_SUB: in getNode()
9763 Opcode = ISD::VP_XOR; in getNode()
9765 case ISD::VP_MUL: in getNode()
9768 Opcode = ISD::VP_AND; in getNode()
9770 case ISD::VP_REDUCE_MUL: in getNode()
9773 Opcode = ISD::VP_REDUCE_AND; in getNode()
9775 case ISD::VP_REDUCE_ADD: in getNode()
9778 Opcode = ISD::VP_REDUCE_XOR; in getNode()
9780 case ISD::VP_REDUCE_SMAX: in getNode()
9781 case ISD::VP_REDUCE_UMIN: in getNode()
9785 Opcode = ISD::VP_REDUCE_AND; in getNode()
9787 case ISD::VP_REDUCE_SMIN: in getNode()
9788 case ISD::VP_REDUCE_UMAX: in getNode()
9792 Opcode = ISD::VP_REDUCE_OR; in getNode()
9844 assert(Op.getOpcode() != ISD::DELETED_NODE && in getNode()
9849 case ISD::SADDO: in getNode()
9850 case ISD::UADDO: in getNode()
9851 case ISD::SSUBO: in getNode()
9852 case ISD::USUBO: { in getNode()
9867 return getNode(ISD::MERGE_VALUES, DL, VTList, {N1, ZeroOverFlow}, Flags); in getNode()
9876 if (Opcode == ISD::UADDO || Opcode == ISD::SADDO) in getNode()
9877 return getNode(ISD::MERGE_VALUES, DL, VTList, in getNode()
9878 {getNode(ISD::XOR, DL, VTList.VTs[0], F1, F2), in getNode()
9879 getNode(ISD::AND, DL, VTList.VTs[1], F1, F2)}, in getNode()
9882 if (Opcode == ISD::USUBO || Opcode == ISD::SSUBO) { in getNode()
9884 return getNode(ISD::MERGE_VALUES, DL, VTList, in getNode()
9885 {getNode(ISD::XOR, DL, VTList.VTs[0], F1, F2), in getNode()
9886 getNode(ISD::AND, DL, VTList.VTs[1], NotF1, F2)}, in getNode()
9892 case ISD::SMUL_LOHI: in getNode()
9893 case ISD::UMUL_LOHI: { in getNode()
9907 if (Opcode == ISD::SMUL_LOHI) { in getNode()
9919 return getNode(ISD::MERGE_VALUES, DL, VTList, {Lo, Hi}, Flags); in getNode()
9923 case ISD::FFREXP: { in getNode()
9935 return getNode(ISD::MERGE_VALUES, DL, VTList, {Result0, Result1}, Flags); in getNode()
9940 case ISD::STRICT_FP_EXTEND: in getNode()
9955 case ISD::STRICT_FP_ROUND: in getNode()
9975 case ISD::SRA_PARTS: in getNode()
9976 case ISD::SRL_PARTS: in getNode()
9977 case ISD::SHL_PARTS: in getNode()
9978 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && in getNode()
9981 else if (N3.getOpcode() == ISD::AND) in getNode()
10450 case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break; in mutateStrictFPToFP()
10452 case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break; in mutateStrictFPToFP()
10835 case ISD::ADD: { in salvageDebugInfo()
10904 case ISD::TRUNCATE: { in salvageDebugInfo()
11441 assert(AllNodes.front().getOpcode() == ISD::EntryToken && in AssignTopologicalOrder()
11480 SDValue TokenFactor = getNode(ISD::TokenFactor, SDLoc(OldChain), MVT::Other, in makeEquivalentMemoryOrdering()
11553 case ISD::ADD: in isNeutralConstant()
11554 case ISD::OR: in isNeutralConstant()
11555 case ISD::XOR: in isNeutralConstant()
11556 case ISD::UMAX: in isNeutralConstant()
11558 case ISD::MUL: in isNeutralConstant()
11560 case ISD::AND: in isNeutralConstant()
11561 case ISD::UMIN: in isNeutralConstant()
11563 case ISD::SMAX: in isNeutralConstant()
11565 case ISD::SMIN: in isNeutralConstant()
11567 case ISD::SUB: in isNeutralConstant()
11568 case ISD::SHL: in isNeutralConstant()
11569 case ISD::SRA: in isNeutralConstant()
11570 case ISD::SRL: in isNeutralConstant()
11572 case ISD::UDIV: in isNeutralConstant()
11573 case ISD::SDIV: in isNeutralConstant()
11578 case ISD::FADD: in isNeutralConstant()
11581 case ISD::FSUB: in isNeutralConstant()
11584 case ISD::FMUL: in isNeutralConstant()
11586 case ISD::FDIV: in isNeutralConstant()
11588 case ISD::FMINNUM: in isNeutralConstant()
11589 case ISD::FMAXNUM: { in isNeutralConstant()
11598 if (Opcode == ISD::FMAXNUM) in isNeutralConstant()
11609 while (V.getOpcode() == ISD::BITCAST) in peekThroughBitcasts()
11615 while (V.getOpcode() == ISD::BITCAST && V.getOperand(0).hasOneUse()) in peekThroughOneUseBitcasts()
11621 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) in peekThroughExtractSubvectors()
11627 while (V.getOpcode() == ISD::TRUNCATE) in peekThroughTruncates()
11633 if (V.getOpcode() != ISD::XOR) in isBitwiseNot()
11659 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstOrConstSplat()
11711 if (N.getOpcode() == ISD::SPLAT_VECTOR) in isConstOrConstSplatFP()
11753 : SDNode(ISD::ADDRSPACECAST, Order, dl, getSDVTList(VT)), in AddrSpaceCastSDNode()
11893 if (getOpcode() == ISD::TokenFactor) { in reachesChainWithoutSideEffects()
11934 SelectionDAG::matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp, in matchBinOpReduction()
11935 ArrayRef<ISD::NodeType> CandidateBinOps, in matchBinOpReduction()
11938 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT || in matchBinOpReduction()
11944 if (llvm::none_of(CandidateBinOps, [Op](ISD::NodeType BinOp) { in matchBinOpReduction()
11955 case ISD::FADD: in matchBinOpReduction()
11974 BinOp = (ISD::NodeType)CandidateBinOp; in matchBinOpReduction()
11975 return getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op, in matchBinOpReduction()
12030 if (Op0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
12031 Op1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
12046 BinOp = (ISD::NodeType)CandidateBinOp; in matchBinOpReduction()
12077 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, in UnrollVectorOp()
12105 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, in UnrollVectorOp()
12119 case ISD::VSELECT: in UnrollVectorOp()
12120 Scalars.push_back(getNode(ISD::SELECT, dl, EltVT, Operands)); in UnrollVectorOp()
12122 case ISD::SHL: in UnrollVectorOp()
12123 case ISD::SRA: in UnrollVectorOp()
12124 case ISD::SRL: in UnrollVectorOp()
12125 case ISD::ROTL: in UnrollVectorOp()
12126 case ISD::ROTR: in UnrollVectorOp()
12131 case ISD::SIGN_EXTEND_INREG: { in UnrollVectorOp()
12150 assert((Opcode == ISD::UADDO || Opcode == ISD::SADDO || in UnrollVectorOverflowOp()
12151 Opcode == ISD::USUBO || Opcode == ISD::SSUBO || in UnrollVectorOverflowOp()
12152 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
12268 getNode(ISD::EXTRACT_ELEMENT, DL, LoVT, N, getIntPtrConstant(0, DL)); in SplitScalar()
12270 getNode(ISD::EXTRACT_ELEMENT, DL, HiVT, N, getIntPtrConstant(1, DL)); in SplitScalar()
12332 getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, getVectorIdxConstant(0, DL)); in SplitVector()
12337 Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N, in SplitVector()
12354 SDValue Lo = getNode(ISD::UMIN, DL, VT, N, HalfNumElts); in SplitEVL()
12355 SDValue Hi = getNode(ISD::USUBSAT, DL, VT, N, HalfNumElts); in SplitEVL()
12364 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
12379 Args.push_back(getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Op, in ExtractVectorElements()
12698 if (Opc != ISD::UNDEF && Opc != ISD::Constant && Opc != ISD::ConstantFP) in isConstant()
12757 if (ISD::isBuildVectorOfConstantSDNodes(N.getNode())) in isConstantIntBuildVectorOrConstantInt()
12762 if (GA->getOpcode() == ISD::GlobalAddress && in isConstantIntBuildVectorOrConstantInt()
12765 if ((N.getOpcode() == ISD::SPLAT_VECTOR) && in isConstantIntBuildVectorOrConstantInt()
12777 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode())) in isConstantFPBuildVectorOrConstantFP()
12780 if ((N.getOpcode() == ISD::SPLAT_VECTOR) && in isConstantFPBuildVectorOrConstantFP()
12816 SDValue NewTF = getNode(ISD::TokenFactor, DL, MVT::Other, ExtractedTFs); in getTokenFactor()
12820 return getNode(ISD::TokenFactor, DL, MVT::Other, Vals); in getTokenFactor()
12828 case ISD::ADD: in getNeutralElement()
12829 case ISD::OR: in getNeutralElement()
12830 case ISD::XOR: in getNeutralElement()
12831 case ISD::UMAX: in getNeutralElement()
12833 case ISD::MUL: in getNeutralElement()
12835 case ISD::AND: in getNeutralElement()
12836 case ISD::UMIN: in getNeutralElement()
12838 case ISD::SMAX: in getNeutralElement()
12840 case ISD::SMIN: in getNeutralElement()
12842 case ISD::FADD: in getNeutralElement()
12844 case ISD::FMUL: in getNeutralElement()
12846 case ISD::FMINNUM: in getNeutralElement()
12847 case ISD::FMAXNUM: { in getNeutralElement()
12853 if (Opcode == ISD::FMAXNUM) in getNeutralElement()
12858 case ISD::FMINIMUM: in getNeutralElement()
12859 case ISD::FMAXIMUM: { in getNeutralElement()
12864 if (Opcode == ISD::FMAXIMUM) in getNeutralElement()