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Searched refs:hasSubClassEq (Results 1 – 25 of 37) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp47 if (X86::GR8RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
48 X86::GR16RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
49 X86::GR32RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
50 X86::GR64RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
51 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
52 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
55 if (X86::FR32XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
56 X86::FR64XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
57 X86::VR128XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
58 X86::VR256XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
[all …]
H A DX86DomainReassignment.cpp45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
H A DX86InstrInfo.cpp3380 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
3381 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
3382 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
3606 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3611 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3613 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3621 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3637 if (X86::GR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3639 if (X86::FR64XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3647 if (X86::VR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp254 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
283 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
285 else if (Mips::LO64RegClass.hasSubClassEq(RC)) in storeRegToStack()
287 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in storeRegToStack()
289 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in storeRegToStack()
291 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) in storeRegToStack()
298 if (Mips::HI32RegClass.hasSubClassEq(RC)) { in storeRegToStack()
332 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
361 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
363 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
[all …]
H A DMips16InstrInfo.cpp116 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
135 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp258 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
271 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
285 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
287 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
289 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
291 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
293 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
295 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
297 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
299 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp635 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
649 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
650 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
3675 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
3679 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
3732 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
3754 if (AArch64::QQQRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
3829 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
3833 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
3886 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1552 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1553 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1554 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1555 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1586 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1867 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1868 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1939 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
1940 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
1994 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in LoadRegFromStackSlot()
[all …]
H A DPPCVSXCopy.cpp54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
H A DPPCVSXSwapRemoval.cpp162 return RC->hasSubClassEq(MRI->getRegClass(Reg)); in isRegInClass()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
459 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
462 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp48 if (!RC.hasSubClassEq(&SubRC)) in verify()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp717 if (M68k::DR8RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
719 if (M68k::CCRCRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
724 assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
727 assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass"); in getLoadStoreRegOpcode()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h120 return RC != this && hasSubClassEq(RC); in hasSubClass()
124 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
137 return RC->hasSubClassEq(this); in hasSuperClassEq()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp177 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
187 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
219 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
228 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
H A DARMBaseInstrInfo.cpp1128 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1139 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1164 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1244 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1270 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1365 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1375 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1397 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1453 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1476 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
H A DThumbRegisterInfo.cpp48 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp925 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
933 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
937 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
941 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
945 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
949 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
970 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
979 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
982 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
985 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
H A DHexagonConstPropagation.cpp2368 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
2370 if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
2372 if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
H A DSystemZInstrInfo.cpp554 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) || in canInsertSelect()
555 SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in canInsertSelect()
556 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in canInsertSelect()
581 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) { in insertSelect()
596 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in insertSelect()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp286 if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp492 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
536 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()

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