Lines Matching refs:hasSubClassEq
258 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
262 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
265 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
268 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
271 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
274 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
277 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
280 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
283 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
285 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
287 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
289 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
291 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
293 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
295 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
297 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
299 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
301 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
303 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
352 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
356 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
359 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
362 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
365 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
368 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
371 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
374 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
377 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
379 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
381 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
383 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
385 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
387 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
389 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
391 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
393 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
395 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
397 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()