551   bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));  in canFoldIntoCSel()
635   if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||  in canInsertSelect()
636       AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in canInsertSelect()
649   if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||  in canInsertSelect()
650       AArch64::FPR32RegClass.hasSubClassEq(RC)) {  in canInsertSelect()
1216     } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&  in UpdateOperandRegClass()
3675     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
3679     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
3681     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3688     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3694     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
3698     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3704     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3706     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3714     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
3716     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3720     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3725     } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3732     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3739     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3743     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3747     } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3754     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3758     } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3765     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3769     } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3829     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
3833     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
3835     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3842     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3848     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
3852     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3858     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3860     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3868     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
3870     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3874     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3879     } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3886     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3893     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3897     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3901     } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3908     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3912     } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3919     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3923     } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()