1128       if (ARM::HPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1139       if (ARM::GPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1146       } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1153       } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1164       if (ARM::DPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1171       } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1192       if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {  in storeRegToStackSlot()
1208       } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&  in storeRegToStackSlot()
1220       if (ARM::DTripleRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1244       if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1270       if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1365     if (ARM::HPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1375     if (ARM::GPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1381     } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1387     } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1397     if (ARM::DPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1403     } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1429     if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {  in loadRegFromStackSlot()
1442     } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&  in loadRegFromStackSlot()
1453     if (ARM::DTripleRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1476     if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1500     if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()