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/freebsd-13.1/crypto/openssl/crypto/bn/asm/
H A Dppc.pl115 $ST= "stw"; # store
139 $ST= "std"; # store
1808 $ST r9,`0*$BNSZ`(r3)
1822 $ST r9,`2*$BNSZ`(r3)
1845 $ST r9,`0*$BNSZ`(r3)
1859 $ST r9,`1*$BNSZ`(r3)
1872 $ST r9,`2*$BNSZ`(r3)
1922 $ST r9,`0*$BNSZ`(r3)
1975 $ST r9,0(r3)
1987 $ST r9,0(r3)
[all …]
H A Dppc-mont.pl55 $ST= "stw"; # store
64 $PUSH= $ST;
76 $ST= "std"; # store
85 $PUSH= $ST;
228 $ST $hi1,$BNSZ($tp)
294 $ST $hi1,$BNSZ($tp)
763 $ST $a1,$SIZE_T*2($tp)
764 $ST $a2,$SIZE_T*3($tp)
765 $ST $a3,$SIZE_T*4($tp)
811 $ST $t0,$SIZE_T*1($bp)
[all …]
H A Dmips.pl64 $ST="sd";
79 $ST="sw";
186 $ST $t1,0($a0)
246 $ST $t1,0($a0)
338 $ST $v0,0($a0)
382 $ST $v0,0($a0)
463 $ST $t1,0($a0)
502 $ST $t1,0($a0)
629 $ST $t0,0($a0)
761 $ST $t0,0($a0)
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp81 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
105 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
113 if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign( in MipsLegalizerInfo()
124 .customIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
139 if (!ST.systemSupportsUnalignedAccess() && in MipsLegalizerInfo()
197 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
240 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
328 verify(*ST.getInstrInfo()); in MipsLegalizerInfo()
473 *ST.getRegBankInfo())) in SelectMSA3OpIntrinsic()
505 const MipsSubtarget &ST = in legalizeIntrinsic() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.h33 const RISCVSubtarget *ST; variable
42 TLI(ST->getTargetLowering()) {} in RISCVTTIImpl()
66 ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0); in getRegisterBitWidth()
69 ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0); in getRegisterBitWidth()
90 return ST->hasStdExtZfh(); in isLegalElementTypeForRVV()
92 return ST->hasStdExtF(); in isLegalElementTypeForRVV()
94 return ST->hasStdExtD(); in isLegalElementTypeForRVV()
100 if (!ST->hasStdExtV()) in isLegalMaskedLoadStore()
122 if (!ST->hasStdExtV()) in isLegalMaskedGatherScatter()
153 if (!ST->hasStdExtV()) in isLegalToVectorizeReduction()
[all …]
/freebsd-13.1/contrib/file/magic/Magdir/
H A Duf229 >>28 lelong 0x00ff6919 ST STM32L4xx
30 >>28 lelong 0x04240bdf ST STM32L5xx
35 >>28 lelong 0x1e1f432d ST STM32L1xx
36 >>28 lelong 0x202e3a91 ST STM32L0xx
37 >>28 lelong 0x21460ff0 ST STM32WLxx
39 >>28 lelong 0x300f5633 ST STM32G0xx
41 >>28 lelong 0x4c71240a ST STM32G4xx
43 >>28 lelong 0x53b80f00 ST STM32F7xx
45 >>28 lelong 0x57755a57 ST STM32F401
47 >>28 lelong 0x5d1a0a2e ST STM32F2xx
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCTargetTransformInfo.h33 const ARCSubtarget *ST; variable
36 const ARCSubtarget *getST() const { return ST; } in getST()
41 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()), in ARCTTIImpl()
42 TLI(ST->getTargetLowering()) {} in ARCTTIImpl()
46 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} in ARCTTIImpl()
48 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), in ARCTTIImpl()
/freebsd-13.1/contrib/llvm-project/llvm/lib/TableGen/
H A DSetTheory.cpp40 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
48 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
54 ST.evaluate(*Expr->arg_begin(), Add, Loc); in apply()
64 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
70 ST.evaluate(Expr->arg_begin()[0], S1, Loc); in apply()
71 ST.evaluate(Expr->arg_begin()[1], S2, Loc); in apply()
83 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
89 ST.evaluate(Expr->arg_begin()[0], Set, Loc); in apply()
94 apply2(ST, Expr, Set, II->getValue(), Elts, Loc); in apply()
165 ST.evaluate(Expr->getArg(i), Args[i], Loc); in apply()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h47 const AArch64Subtarget *ST; variable
50 const AArch64Subtarget *getST() const { return ST; } in getST()
65 TLI(ST->getTargetLowering()) {} in AArch64TTIImpl()
96 if (ST->hasNEON()) in getNumberOfRegisters()
114 if (ST->hasSVE()) in getRegisterBitWidth()
117 return TypeSize::getFixed(ST->hasNEON() ? 128 : 0); in getRegisterBitWidth()
125 return ST->getMinVectorRegisterBitWidth(); in getMinVectorRegisterBitWidth()
129 if (ST->hasSVE()) in getMaxVScale()
226 if (Ty->isBFloatTy() && ST->hasBF16()) in isElementTypeLegalForScalableVector()
240 if (!ST->hasSVE()) in isLegalMaskedLoadStore()
[all …]
H A DAArch64StackTaggingPreRA.cpp267 SlotWithTag ST{*I}; in findFirstSlotCandidate() local
268 if (isSlotPreAllocated(MFI, ST.FI)) in findFirstSlotCandidate()
296 LLVM_DEBUG(dbgs() << "[" << ST.FI << ":" << ST.Tag << "] use of %" in findFirstSlotCandidate()
303 int TotalScore = RetagScore[ST] += Score; in findFirstSlotCandidate()
307 MaxScoreST = ST; in findFirstSlotCandidate()
321 SlotWithTag ST{*I}; in findFirstSlotCandidate() local
322 if (ST.Tag == 0) { in findFirstSlotCandidate()
323 SwapST = ST; in findFirstSlotCandidate()
332 SlotWithTag ST{*I}; in findFirstSlotCandidate() local
334 if (ST == MaxScoreST) { in findFirstSlotCandidate()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNIterativeScheduler.cpp94 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in printRegions() local
100 R->MaxPressure.print(OS, &ST); in printRegions()
118 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in printSchedRP() local
120 Before.print(OS, &ST); in printSchedRP()
122 After.print(OS, &ST); in printSchedRP()
409 SchedMaxRP.print(dbgs(), &ST), in scheduleRegion()
411 MaxRP.print(dbgs(), &ST), in scheduleRegion()
413 RegionMaxRP.print(dbgs(), &ST), in scheduleRegion()
443 if (R->MaxPressure.getOccupancy(ST) >= NewOcc) in tryMaximizeOccupancy()
505 if (RP.getOccupancy(ST) < TgtOcc) { in scheduleLegacyMaxOccupancy()
[all …]
H A DSIMachineFunctionInfo.cpp56 WavesPerEU = ST.getWavesPerEU(F); in SIMachineFunctionInfo()
88 if (!ST.enableFlatScratch()) { in SIMachineFunctionInfo()
142 if (!ST.flatScratchIsArchitected()) { in SIMachineFunctionInfo()
153 bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F); in SIMachineFunctionInfo()
155 if (!ST.enableFlatScratch()) in SIMachineFunctionInfo()
174 } else if (ST.isMesaGfxShader(F)) { in SIMachineFunctionInfo()
187 !ST.flatScratchIsArchitected()) { in SIMachineFunctionInfo()
282 unsigned WaveSize = ST.getWavefrontSize(); in haveFreeLanesForSGPRSpill()
299 unsigned WaveSize = ST.getWavefrontSize(); in allocateSGPRSpillToVGPR()
496 if (!ST.isAmdPalOS()) in getGITPtrLoReg()
[all …]
H A DSIFrameLowering.cpp212 if (ST.isAmdPalOS()) { in emitEntryFunctionFlatScratchInit()
278 if (ST.flatScratchIsPointer()) { in emitEntryFunctionFlatScratchInit()
356 if (ST.hasSGPRInitBug() || in getEntryFunctionReservedScratchRsrcReg()
392 return ST.enableFlatScratch() ? 1 : ST.getWavefrontSize(); in getScratchScaleFactor()
433 if (!ST.enableFlatScratch()) in emitEntryFunctionPrologue()
448 if (ST.isAmdHsaOrMesa(F)) { in emitEntryFunctionPrologue()
537 if (ST.isAmdPalOS()) { in emitEntryFunctionScratchRsrcRegSetup()
571 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
578 assert(!ST.isAmdHsaOrMesa(Fn)); in emitEntryFunctionScratchRsrcRegSetup()
636 } else if (ST.isAmdHsaOrMesa(Fn)) { in emitEntryFunctionScratchRsrcRegSetup()
[all …]
H A DGCNHazardRecognizer.cpp34 TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
39 TSchedModel.init(&ST); in GCNHazardRecognizer()
170 if (ST.hasNoDataDepHazard()) in getHazardType()
282 if (ST.hasNSAtoVMEMBug()) in PreEmitNoopsCommon()
287 if (ST.hasNoDataDepHazard()) in PreEmitNoopsCommon()
525 if (!ST.isXNACKEnabled()) in checkSoftClauseHazards()
850 if (!ST.hasRFEHazards()) in checkRFEHazards()
1165 if (!ST.hasNSAtoVMEMBug()) in checkNSAtoVMEMHazard()
1486 if (!isXDL(ST, *MI)) in checkMAIHazards90A()
1553 if (!ST.hasMAIInsts() || ST.hasGFX90AInsts()) in checkMAILdStHazards()
[all …]
H A DAMDGPUTargetTransformInfo.cpp101 TLI(ST->getTargetLowering()) {} in AMDGPUTTIImpl()
290 MaxVGPRs(ST->getMaxNumVGPRs( in GCNTTIImpl()
291 std::max(ST->getWavesPerEU(F).first, in GCNTTIImpl()
292 ST->getWavesPerEUForWorkGroup( in GCNTTIImpl()
373 return 8 * ST->getMaxPrivateElementSize(); in getLoadStoreVecRegBitWidth()
590 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
605 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
616 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
651 if (ST->has16BitInsts() && SLT == MVT::f16) in getArithmeticInstrCost()
1137 if (ST->hasVOP3PInsts()) { in getShuffleCost()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp112 if (ST->isMClass() && ST->isThumb2() && in getPreferredAddressingMode()
261 if (!ST->isThumb()) { in getIntImmCost()
268 if (ST->isThumb2()) { in getIntImmCost()
376 if (Inst && ((ST->hasV6Ops() && !ST->isThumb()) || ST->isThumb2()) && in getIntImmCostInst()
391 (ST->hasNEON() || ST->hasMVEIntegerOps())) { in getCFInstrCost()
997 if (ST->hasNEON()) { in getAddressComputationCost()
1150 if (ST->hasNEON()) { in getShuffleCost()
1273 if (ST->hasNEON()) { in getArithmeticInstrCost()
1475 ST->hasMVEIntegerOps() ? ST->getMVEVectorCostFactor(CostKind) : 1; in getInterleavedMemoryOpCost()
1745 return !ST->hasFPARMv8Base() && !ST->hasVFP2Base(); in isLoweredToCall()
[all …]
H A DARMTargetTransformInfo.h62 const ARMSubtarget *ST; variable
98 const ARMSubtarget *getST() const { return ST; } in getST()
104 TLI(ST->getTargetLowering()) {} in ARMTTIImpl()
118 return !ST->isTargetDarwin() && !ST->hasMVEFloatOps(); in isFPVectorizationPotentiallyUnsafe()
147 if (ST->hasNEON()) in getNumberOfRegisters()
149 if (ST->hasMVEIntegerOps()) in getNumberOfRegisters()
154 if (ST->isThumb1Only()) in getNumberOfRegisters()
164 if (ST->hasNEON()) in getRegisterBitWidth()
166 if (ST->hasMVEIntegerOps()) in getRegisterBitWidth()
176 return ST->getMaxInterleaveFactor(); in getMaxInterleaveFactor()
[all …]
H A DARMSLSHardening.cpp38 const ARMSubtarget *ST; member in __anon3a18fb6b0111::ARMSLSHardening
70 static void insertSpeculationBarrier(const ARMSubtarget *ST, in insertSpeculationBarrier() argument
82 const TargetInstrInfo *TII = ST->getInstrInfo(); in insertSpeculationBarrier()
83 assert(ST->hasDataBarrier() || ST->hasSB()); in insertSpeculationBarrier()
84 bool ProduceSB = ST->hasSB() && !AlwaysUseISBDSB; in insertSpeculationBarrier()
86 ProduceSB ? (ST->isThumb() ? ARM::t2SpeculationBarrierSBEndBB in insertSpeculationBarrier()
88 : (ST->isThumb() ? ARM::t2SpeculationBarrierISBDSBEndBB in insertSpeculationBarrier()
95 ST = &MF.getSubtarget<ARMSubtarget>(); in runOnMachineFunction()
108 if (!ST->hardenSlsRetBr()) in hardenReturnsAndBRs()
110 assert(!ST->isThumb1Only()); in hardenReturnsAndBRs()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSectionXCOFF.h43 XCOFF::SymbolType ST, SectionKind K, MCSymbolXCOFF *QualName, in MCSectionXCOFF() argument
47 CsectProp(XCOFF::CsectProperties(SMC, ST)), QualName(QualName), in MCSectionXCOFF()
51 (ST == XCOFF::XTY_SD || ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
55 assert((ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
61 if (ST != XCOFF::XTY_ER) in MCSectionXCOFF()
/freebsd-13.1/crypto/openssl/crypto/rc4/asm/
H A Drc4-parisc.pl71 $ST="stb";
76 $ST="stw";
107 $ST $TX[0],0($ix)
111 $ST $TY,0($iy)
127 $ST $TX[0],0($iy)
129 $ST $TY,0($ix)
259 $ST %r0,`0*$SZ`($key)
260 $ST %r0,`1*$SZ`($key)
264 $ST @XX[0],0($key)
288 $ST @TX[0],0($YY)
[all …]
/freebsd-13.1/crypto/openssl/crypto/sha/asm/
H A Dsha512-s390x.pl81 $ST="stg"; # store to memory
95 $ST="st"; # store to memory
124 $ST $T1,`$stdframe+$SZ*($i%16)`($sp)
302 $ST $A,`0*$SZ`($ctx)
303 $ST $B,`1*$SZ`($ctx)
304 $ST $C,`2*$SZ`($ctx)
305 $ST $D,`3*$SZ`($ctx)
306 $ST $E,`4*$SZ`($ctx)
307 $ST $F,`5*$SZ`($ctx)
308 $ST $G,`6*$SZ`($ctx)
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MacroFusion.cpp38 const X86Subtarget &ST = static_cast<const X86Subtarget &>(TSI); in shouldScheduleAdjacent() local
41 if (!(ST.hasBranchFusion() || ST.hasMacroFusion())) in shouldScheduleAdjacent()
54 if (ST.hasBranchFusion()) { in shouldScheduleAdjacent()
60 if (ST.hasMacroFusion()) { in shouldScheduleAdjacent()
H A DX86TargetTransformInfo.cpp165 if (ST->isAtom()) in getMaxInterleaveFactor()
170 if (ST->hasAVX()) in getMaxInterleaveFactor()
244 if (ST->isSLM()) { in getArithmeticInstrCost()
395 ST->hasSSE2() && !ST->hasXOP()) { in getArithmeticInstrCost()
531 if (ST->hasBWI()) in getArithmeticInstrCost()
588 if (ST->hasDQI()) in getArithmeticInstrCost()
599 if (ST->hasBWI()) in getArithmeticInstrCost()
4497 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) in getGatherOverhead()
4674 return ST->hasMacroFusion() || ST->hasBranchFusion(); in canMacroFuseCmp()
4711 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); in isLegalNTLoad()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.cpp25 auto &ST = DAG.getMachineFunction().getSubtarget<WebAssemblySubtarget>(); in EmitTargetCodeForMemcpy() local
26 if (!ST.hasBulkMemory()) in EmitTargetCodeForMemcpy()
30 auto LenMVT = ST.hasAddr64() ? MVT::i64 : MVT::i32; in EmitTargetCodeForMemcpy()
49 auto &ST = DAG.getMachineFunction().getSubtarget<WebAssemblySubtarget>(); in EmitTargetCodeForMemset() local
50 if (!ST.hasBulkMemory()) in EmitTargetCodeForMemset()
54 auto LenMVT = ST.hasAddr64() ? MVT::i64 : MVT::i32; in EmitTargetCodeForMemset()
/freebsd-13.1/stand/efi/boot1/
H A Dboot1.c165 ST = Xsystab; in efi_main()
167 BS = ST->BootServices; in efi_main()
168 RS = ST->RuntimeServices; in efi_main()
174 ST->ConOut->OutputString(ST->ConOut, in efi_main()
192 conout = ST->ConOut; in efi_main()
319 ST->ConOut->OutputString(ST->ConOut, buf); in putchar()
323 ST->ConOut->OutputString(ST->ConOut, buf); in putchar()

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