100       ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))),  in AMDGPUTTIImpl()
101       TLI(ST->getTargetLowering()) {}  in AMDGPUTTIImpl()
287       ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))),  in GCNTTIImpl()
288       TLI(ST->getTargetLowering()), CommonTTI(TM, F),  in GCNTTIImpl()
290       MaxVGPRs(ST->getMaxNumVGPRs(  in GCNTTIImpl()
291           std::max(ST->getWavesPerEU(F).first,  in GCNTTIImpl()
292                    ST->getWavesPerEUForWorkGroup(  in GCNTTIImpl()
293                        ST->getFlatWorkGroupSizes(F).second)))) {  in GCNTTIImpl()
312   const SIRegisterInfo *TRI = ST->getRegisterInfo();  in getNumberOfRegisters()
324     return TypeSize::getFixed(ST->hasPackedFP32Ops() ? 64 : 32);  in getRegisterBitWidth()
338   return (ElemWidth == 16 && ST->has16BitInsts()) ? 2  in getMaximumVF()
339        : (ElemWidth == 32 && ST->hasPackedFP32Ops()) ? 2  in getMaximumVF()
373     return 8 * ST->getMaxPrivateElementSize();  in getLoadStoreVecRegBitWidth()
386     return (Alignment >= 4 || ST->hasUnalignedScratchAccess()) &&  in isLegalToVectorizeMemChain()
387       ChainSizeInBytes <= ST->getMaxPrivateElementSize();  in isLegalToVectorizeMemChain()
590     if (ST->has16BitInsts() && SLT == MVT::i16)  in getArithmeticInstrCost()
605     if (ST->has16BitInsts() && SLT == MVT::i16)  in getArithmeticInstrCost()
616     if (ST->has16BitInsts() && SLT == MVT::i16)  in getArithmeticInstrCost()
630           if (ST->hasMadMacF32Insts() && SLT == MVT::f32 && !HasFP32Denormals)  in getArithmeticInstrCost()
632           if (ST->has16BitInsts() && SLT == MVT::f16 && !HasFP64FP16Denormals)  in getArithmeticInstrCost()
646     if (ST->hasPackedFP32Ops() && SLT == MVT::f32)  in getArithmeticInstrCost()
651     if (ST->has16BitInsts() && SLT == MVT::f16)  in getArithmeticInstrCost()
666       if (!ST->hasUsableDivScaleConditionOutput())  in getArithmeticInstrCost()
675           (SLT == MVT::f16 && ST->has16BitInsts())) {  in getArithmeticInstrCost()
680     if (SLT == MVT::f16 && ST->has16BitInsts()) {  in getArithmeticInstrCost()
789   if ((ST->has16BitInsts() && SLT == MVT::f16) ||  in getIntrinsicInstrCost()
790       (ST->hasPackedFP32Ops() && SLT == MVT::f32))  in getIntrinsicInstrCost()
798     InstRate = ST->hasFastFMAF32() ? getHalfRateInstrCost(CostKind)  in getIntrinsicInstrCost()
855   if (!ST->hasVOP3PInsts() || OrigTy.getScalarSizeInBits() != 16)  in getArithmeticReductionCost()
870   if (!ST->hasVOP3PInsts() || OrigTy.getScalarSizeInBits() != 16)  in getMinMaxReductionCost()
885       if (EltSize == 16 && Index == 0 && ST->has16BitInsts())  in getVectorInstrCost()
913   const SIRegisterInfo *TRI = ST->getRegisterInfo();  in isInlineAsmSourceOfDivergence()
915       TLI->ParseConstraints(DL, ST->getRegisterInfo(), *CI);  in isInlineAsmSourceOfDivergence()
1137   if (ST->hasVOP3PInsts()) {  in getShuffleCost()
1237   return ST->hasFullRate64Ops()  in get64BitInstrCost()
1239              : ST->hasHalfRate64Ops() ? getHalfRateInstrCost(CostKind)  in get64BitInstrCost()
1245       ST(static_cast<const R600Subtarget *>(TM->getSubtargetImpl(F))),  in R600TTIImpl()
1246       TLI(ST->getTargetLowering()), CommonTTI(TM, F) {}  in R600TTIImpl()