Lines Matching refs:ST
67 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getVGPRSpillLaneOrTempRegister() local
68 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in getVGPRSpillLaneOrTempRegister()
124 static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI, in buildPrologSpill() argument
130 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in buildPrologSpill()
145 static void buildEpilogRestore(const GCNSubtarget &ST, in buildEpilogRestore() argument
152 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in buildEpilogRestore()
194 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit() local
195 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEntryFunctionFlatScratchInit()
212 if (ST.isAmdPalOS()) { in emitEntryFunctionFlatScratchInit()
278 if (ST.flatScratchIsPointer()) { in emitEntryFunctionFlatScratchInit()
279 if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) { in emitEntryFunctionFlatScratchInit()
308 assert(ST.getGeneration() < AMDGPUSubtarget::GFX9); in emitEntryFunctionFlatScratchInit()
342 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getEntryFunctionReservedScratchRsrcReg() local
343 const SIInstrInfo *TII = ST.getInstrInfo(); in getEntryFunctionReservedScratchRsrcReg()
356 if (ST.hasSGPRInitBug() || in getEntryFunctionReservedScratchRsrcReg()
391 static unsigned getScratchScaleFactor(const GCNSubtarget &ST) { in getScratchScaleFactor() argument
392 return ST.enableFlatScratch() ? 1 : ST.getWavefrontSize(); in getScratchScaleFactor()
411 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionPrologue() local
412 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEntryFunctionPrologue()
433 if (!ST.enableFlatScratch()) in emitEntryFunctionPrologue()
448 if (ST.isAmdHsaOrMesa(F)) { in emitEntryFunctionPrologue()
494 .addImm(FrameInfo.getStackSize() * getScratchScaleFactor(ST)); in emitEntryFunctionPrologue()
506 (!allStackObjectsAreDead(FrameInfo) && ST.enableFlatScratch())); in emitEntryFunctionPrologue()
509 !ST.flatScratchIsArchitected()) { in emitEntryFunctionPrologue()
531 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionScratchRsrcRegSetup() local
532 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEntryFunctionScratchRsrcRegSetup()
537 if (ST.isAmdPalOS()) { in emitEntryFunctionScratchRsrcRegSetup()
571 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
577 } else if (ST.isMesaGfxShader(Fn) || !PreloadedScratchRsrcReg) { in emitEntryFunctionScratchRsrcRegSetup()
578 assert(!ST.isAmdHsaOrMesa(Fn)); in emitEntryFunctionScratchRsrcRegSetup()
636 } else if (ST.isAmdHsaOrMesa(Fn)) { in emitEntryFunctionScratchRsrcRegSetup()
706 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in buildScratchExecCopy() local
707 const SIInstrInfo *TII = ST.getInstrInfo(); in buildScratchExecCopy()
722 ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64; in buildScratchExecCopy()
745 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitPrologue() local
746 const SIInstrInfo *TII = ST.getInstrInfo(); in emitPrologue()
779 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR, in emitPrologue()
794 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, VGPR, *FI); in emitPrologue()
799 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitPrologue()
800 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitPrologue()
820 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitPrologue()
838 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitPrologue()
928 .addImm((Alignment - 1) * getScratchScaleFactor(ST)) in emitPrologue()
932 .addImm(-Alignment * getScratchScaleFactor(ST)) in emitPrologue()
954 .addImm(RoundedSize * getScratchScaleFactor(ST)) in emitPrologue()
981 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEpilogue() local
982 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEpilogue()
1005 .addImm(-static_cast<int64_t>(RoundedSize * getScratchScaleFactor(ST))) in emitEpilogue()
1031 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitEpilogue()
1057 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitEpilogue()
1083 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR, in emitEpilogue()
1097 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, VGPR, *FI); in emitEpilogue()
1102 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitEpilogue()
1103 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitEpilogue()
1141 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in processFunctionBeforeFrameFinalized() local
1142 const SIInstrInfo *TII = ST.getInstrInfo(); in processFunctionBeforeFrameFinalized()
1143 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in processFunctionBeforeFrameFinalized()
1147 const bool SpillVGPRToAGPR = ST.hasMAIInsts() && FuncInfo->hasSpilledVGPRs() in processFunctionBeforeFrameFinalized()
1234 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in determineCalleeSaves() local
1235 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in determineCalleeSaves()
1243 if (!ST.hasGFX90AInsts()) in determineCalleeSaves()
1292 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in determineCalleeSavesSGPR() local
1293 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in determineCalleeSavesSGPR()
1325 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in assignCalleeSavedSpillSlots() local
1326 const SIRegisterInfo *RI = ST.getRegisterInfo(); in assignCalleeSavedSpillSlots()
1360 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in eliminateCallFramePseudoInstr() local
1361 const SIInstrInfo *TII = ST.getInstrInfo(); in eliminateCallFramePseudoInstr()
1373 Amount *= getScratchScaleFactor(ST); in eliminateCallFramePseudoInstr()