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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 if (RC == &NVPTX::Float32RegsRegClass) in getNVPTXRegClassName()
31 if (RC == &NVPTX::Float16RegsRegClass) in getNVPTXRegClassName()
39 if (RC == &NVPTX::Float64RegsRegClass) in getNVPTXRegClassName()
41 if (RC == &NVPTX::Int64RegsRegClass) in getNVPTXRegClassName()
61 if (RC == &NVPTX::Int32RegsRegClass) in getNVPTXRegClassName()
63 if (RC == &NVPTX::Int16RegsRegClass) in getNVPTXRegClassName()
65 if (RC == &NVPTX::Int1RegsRegClass) in getNVPTXRegClassName()
81 if (RC == &NVPTX::Int64RegsRegClass) in getNVPTXRegClassStr()
83 if (RC == &NVPTX::Int32RegsRegClass) in getNVPTXRegClassStr()
85 if (RC == &NVPTX::Int16RegsRegClass) in getNVPTXRegClassStr()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp89 if (RC == &WebAssembly::I32RegClass) in getDropOpcode()
91 if (RC == &WebAssembly::I64RegClass) in getDropOpcode()
93 if (RC == &WebAssembly::F32RegClass) in getDropOpcode()
95 if (RC == &WebAssembly::F64RegClass) in getDropOpcode()
108 if (RC == &WebAssembly::I32RegClass) in getLocalGetOpcode()
110 if (RC == &WebAssembly::I64RegClass) in getLocalGetOpcode()
112 if (RC == &WebAssembly::F32RegClass) in getLocalGetOpcode()
114 if (RC == &WebAssembly::F64RegClass) in getLocalGetOpcode()
127 if (RC == &WebAssembly::I32RegClass) in getLocalSetOpcode()
129 if (RC == &WebAssembly::I64RegClass) in getLocalSetOpcode()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp93 unsigned ID = RC.getID(); in mask()
119 if (RC.contains(Reg)) in getPhysRegBitWidth()
133 return RC; in composeWithSubRegIndex()
142 switch (RC.getID()) { in composeWithSubRegIndex()
278 return eXTR(RC, 0, RW); in evaluate()
283 uint16_t W = RC.width(); in evaluate()
304 return RC; in evaluate()
691 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
793 RegisterCell RC(WR); in evaluate() local
889 RegisterCell RC(W0); in evaluate() local
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H A DBitTracker.h327 return !operator==(RC);
365 RegisterCell RC(Width); in self()
368 return RC; in self()
373 RegisterCell RC(Width); in top()
376 return RC; in top()
382 RegisterCell RC(W); in ref()
384 RC[i] = BitValue::ref(C[i]); in ref()
385 return RC; in ref()
406 RegisterCell RC = getCell(RR, M); in getRef() local
407 return RegisterCell::ref(RC); in getRef()
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/freebsd-13.1/contrib/ofed/libibverbs/
H A Dopcode.h83 IBV_OPCODE(RC, SEND_FIRST),
84 IBV_OPCODE(RC, SEND_MIDDLE),
85 IBV_OPCODE(RC, SEND_LAST),
87 IBV_OPCODE(RC, SEND_ONLY),
89 IBV_OPCODE(RC, RDMA_WRITE_FIRST),
90 IBV_OPCODE(RC, RDMA_WRITE_MIDDLE),
91 IBV_OPCODE(RC, RDMA_WRITE_LAST),
93 IBV_OPCODE(RC, RDMA_WRITE_ONLY),
100 IBV_OPCODE(RC, ACKNOWLEDGE),
102 IBV_OPCODE(RC, COMPARE_SWAP),
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
61 (ins RC:$src1, RC:$src2, RC:$src3),
81 (ins RC:$src1, RC:$src2, RC:$src3),
182 (ins RC:$src1, RC:$src2, RC:$src3),
185 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>,
203 (ins RC:$src1, RC:$src2, RC:$src3),
223 (ins RC:$src1, RC:$src2, RC:$src3),
395 (ins RC:$src1, RC:$src2, RC:$src3),
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H A DX86InstrAVX512.td678 Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
1704 (ins _.RC:$src2, _.RC:$src3),
1706 (_.VT (X86VPermt2 _.RC:$src2, IdxVT.RC:$src1, _.RC:$src3)), 1>,
1828 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3)), 1>,
3917 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2)))],
3929 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
5136 _.RC:$src1, _.RC:$src2)>;
6401 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
6402 (_.VT (MaskOpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)), 1, 1>,
6992 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1>,
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H A DX86InstrXOP.td332 (ins RC:$src1, RC:$src2, RC:$src3),
335 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
341 (ins RC:$src1, RC:$src2, x86memop:$src3),
347 (ins RC:$src1, x86memop:$src2, RC:$src3),
350 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
361 (ins RC:$src1, RC:$src2, RC:$src3),
421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4),
436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4),
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/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp74 if (llvm::is_contained(RCs, RC)) in addRegisterClass()
84 RCWithLargestRegsSize = RC; in addRegisterClass()
87 RCWithLargestRegsSize = RC; in addRegisterClass()
90 RCs.emplace_back(RC); in addRegisterClass()
176 if (VisitedRCs.count(RC)) in visitRegisterBankClasses()
178 VisitedRCs.insert(RC); in visitRegisterBankClasses()
181 VisitFn(RC, Kind.str()); in visitRegisterBankClasses()
188 if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass)) in visitRegisterBankClasses()
224 RCsGroupedByWord[RC->EnumValue / 32].push_back(RC); in emitBaseClassImplementation()
230 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
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H A DRegisterInfoEmitter.cpp146 for (const auto &RC : RegisterClasses) in runEnums() local
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
1081 if (RC.RSI.isSimple()) in runMCDesc()
1083 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1084 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1230 if (RC.Allocatable) in runTargetDesc()
1295 << RC.getName() << '\n'; in runTargetDesc()
1372 if (!RC.AltOrderSelect.empty()) { in runTargetDesc()
1392 if (RC.getOrder(oi).empty()) in runTargetDesc()
1412 printMask(OS, RC.LaneMask); in runTargetDesc()
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H A DCodeGenRegisters.cpp949 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
978 if (&*I == &RC) in computeSubClasses()
988 if (!RC.getDef()) in computeSubClasses()
1138 getReg(RC); in CodeGenRegBank()
1279 return RC; in getRegClass()
1894 if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet) in computeRegUnitSets()
2211 RC->setSubClassWithSubReg(&SubIdx, RC); in inferSubClassWithSubReg()
2240 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
2284 getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" + in inferMatchingSuperRegClass()
2388 RC.contains(Reg) && (!BestRC || BestRC->hasSubClass(&RC))) in getMinimalPhysRegClass()
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h73 void compute(const TargetRegisterClass *RC) const;
76 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
77 const RCInfo &RCI = RegClass[RC->getID()]; in get()
79 compute(RC); in get()
93 return get(RC).NumRegs; in getNumAllocatableRegs()
100 return get(RC); in getOrder()
109 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass() argument
110 return get(RC).ProperSubClass; in isProperSubClass()
125 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost() argument
126 return get(RC).MinCost; in getMinCost()
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H A DTargetRegisterInfo.h120 return RC != this && hasSubClassEq(RC); in hasSubClass()
125 unsigned ID = RC->getID(); in hasSubClassEq()
132 return RC->hasSubClass(this); in hasSuperClass()
137 return RC->hasSubClassEq(this); in hasSuperClassEq()
275 return getRegClassInfo(RC).RegSize; in getRegSizeInBits()
281 return getRegClassInfo(RC).SpillSize / 8; in getSpillSize()
314 return getRegClassInfo(RC).VTList; in legalclasstypes_begin()
613 return RC; in getSubClassWithSubReg()
767 return RC; in getCrossCopyRegClass()
779 return RC; in getLargestLegalSuperClass()
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/freebsd-13.1/sys/ofed/include/rdma/
H A Dib_pack.h117 IB_OPCODE(RC, SEND_FIRST),
118 IB_OPCODE(RC, SEND_MIDDLE),
119 IB_OPCODE(RC, SEND_LAST),
121 IB_OPCODE(RC, SEND_ONLY),
123 IB_OPCODE(RC, RDMA_WRITE_FIRST),
124 IB_OPCODE(RC, RDMA_WRITE_MIDDLE),
125 IB_OPCODE(RC, RDMA_WRITE_LAST),
127 IB_OPCODE(RC, RDMA_WRITE_ONLY),
134 IB_OPCODE(RC, ACKNOWLEDGE),
136 IB_OPCODE(RC, COMPARE_SWAP),
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp93 assert(RC && "no register class given"); in compute()
94 RCInfo &RCI = RegClass[RC->getID()]; in compute()
98 unsigned NumRegs = RC->getNumRegs(); in compute()
150 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
172 const TargetRegisterClass *RC = nullptr; in computePSetLimit() local
186 if (!RC || NUnits > NumRCUnits) { in computePSetLimit()
187 RC = C; in computePSetLimit()
191 assert(RC && "Failed to find register class"); in computePSetLimit()
192 compute(RC); in computePSetLimit()
193 unsigned NAllocatableRegs = getNumAllocatableRegs(RC); in computePSetLimit()
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H A DTargetRegisterInfo.cpp195 if (!RC || RC->isAllocatable()) in getAllocatableClass()
196 return RC; in getAllocatableClass()
220 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC))) in getMinimalPhysRegClass()
221 BestRC = RC; in getMinimalPhysRegClass()
237 if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) && in getMinimalPhysRegClassLLT()
239 BestRC = RC; in getMinimalPhysRegClassLLT()
258 if (RC) { in getAllocatableSet()
354 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
367 BestRC = RC; in getCommonSuperRegClass()
517 RC = MRI.getRegClass(Reg); in getRegSizeInBits()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
43 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
45 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
46 TRI.getSpillAlign(RC), true); in createLRSpillSlot()
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
60 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
72 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
73 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
268 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
269 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
273 PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),
274 [(set RC:$dst, (MipsCMovFP_T RC:$T, FCCRegsOpnd:$cond, RC:$F))]>,
278 PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),
303 PseudoSE<(outs RC:$dst1, RC:$dst2),
[all …]
H A DMipsInstrFPU.td113 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
204 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
206 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
211 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
213 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
260 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
986 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)),
987 (Nmadd RC:$fr, RC:$fs, RC:$ft)>;
988 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)),
[all …]
H A DMipsMachineFunction.cpp71 const TargetRegisterClass *RC; in initGlobalBaseReg() local
74 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
76 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
77 Register V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
152 const TargetRegisterClass &RC = in createEhDataRegsFI() local
158 TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false); in createEhDataRegsFI()
167 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
172 TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false); in createISRRegFI()
194 const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI() argument
198 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false); in getMoveF64ViaSpillFI()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DCGSCCPassManager.cpp298 RC = UR.UpdatedRC ? UR.UpdatedRC : RC; in run()
631 for (auto &C : RC) { in invalidate()
902 RefSCC *RC = &InitialRC; in updateCGAndAnalysisManagerForPass() local
983 assert((RC == &TargetRC || in updateCGAndAnalysisManagerForPass()
1042 if (&TargetRC == RC) in updateCGAndAnalysisManagerForPass()
1090 if (&TargetRC != RC) { in updateCGAndAnalysisManagerForPass()
1126 if (&TargetRC != RC) { in updateCGAndAnalysisManagerForPass()
1144 auto InitialSCCIndex = RC->find(*C) - RC->begin(); in updateCGAndAnalysisManagerForPass()
1185 auto NewSCCIndex = RC->find(*C) - RC->begin(); in updateCGAndAnalysisManagerForPass()
1218 if (RC != &InitialRC) in updateCGAndAnalysisManagerForPass()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h154 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass() argument
155 return !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()
166 bool isAGPRClass(const TargetRegisterClass *RC) const { in isAGPRClass() argument
167 return hasAGPRs(RC) && !hasVGPRs(RC); in isAGPRClass()
171 bool hasVGPRs(const TargetRegisterClass *RC) const;
174 bool hasAGPRs(const TargetRegisterClass *RC) const;
177 bool hasVectorRegisters(const TargetRegisterClass *RC) const { in hasVectorRegisters() argument
178 return hasVGPRs(RC) || hasAGPRs(RC); in hasVectorRegisters()
223 const TargetRegisterClass *RC,
238 return !isSGPRClass(RC); in isDivergentRegClass()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td109 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
214 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
351 def _v : RR<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
422 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
560 defm vv : RVmm<opcStr, ", $vy, $vz", opc, RC, RCM, (ins RC:$vy, RC:$vz)>;
572 defm v : RVmm<opcStr, ", $vz", opc, RC, RCM, (ins RC:$vz)>;
588 defm vv : RVmm<opcStr, ", $vz, $vy", opc, RC, RCM, (ins RC:$vz, RC:$vy)>;
601 (ins RC:$vy, RC:$vz, I64:$sy)>;
604 (ins RC:$vy, RC:$vz, uimm7:$sy)>;
630 defm v : RVmm<opcStr, ", $vy", opc, RC, RCM, (ins RC:$vy)>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
37 if (!covers(RC)) in verify()
48 if (!RC.hasSubClassEq(&SubRC)) in verify()
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
63 return ContainedRegClasses.test(RC.getID()); in covers()
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
107 if (covers(RC)) in print()
108 OS << LS << TRI->getRegClassName(&RC); in print()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp619 const TargetRegisterClass *RC = in canInsertSelect() local
621 if (!RC) in canInsertSelect()
748 RC = &AArch64::GPR64RegClass; in insertSelect()
752 RC = &AArch64::GPR32RegClass; in insertSelect()
756 RC = &AArch64::FPR64RegClass; in insertSelect()
759 RC = &AArch64::FPR32RegClass; in insertSelect()
5265 const TargetRegisterClass *RC; in genAlternativeCodeSequence() local
5441 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
5446 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
5461 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
[all …]

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