Lines Matching refs:RC
146 for (const auto &RC : RegisterClasses) in runEnums() local
147 OS << " " << RC.getName() << "RegClassID" in runEnums()
148 << " = " << RC.EnumValue << ",\n"; in runEnums()
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure()
219 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure()
227 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
1041 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1042 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
1045 const std::string &Name = RC.getName(); in runMCDesc()
1078 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1079 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); in runMCDesc()
1081 if (RC.RSI.isSimple()) in runMCDesc()
1082 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1083 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1084 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1085 << ", sizeof(" << RC.getName() << "Bits), " in runMCDesc()
1086 << RC.getQualifiedName() + "RegClassID" in runMCDesc()
1087 << ", " << RegSize << ", " << RC.CopyCost << ", " in runMCDesc()
1088 << (RC.Allocatable ? "true" : "false") << " },\n"; in runMCDesc()
1190 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1191 const std::string &Name = RC.getName(); in runTargetHeader()
1227 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1228 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1230 if (RC.Allocatable) in runTargetDesc()
1240 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1242 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1284 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1285 assert(RC.EnumValue == EV && "Unexpected order of register classes"); in runTargetDesc()
1288 const RegSizeInfo &RI = RC.RSI.get(M); in runTargetDesc()
1292 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1295 << RC.getName() << '\n'; in runTargetDesc()
1328 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1329 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1331 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1335 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; in runTargetDesc()
1338 RC.getSuperRegClasses(&Idx, MaskBV); in runTargetDesc()
1356 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1357 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); in runTargetDesc()
1364 << RC.getName() << "Superclasses[] = {\n"; in runTargetDesc()
1371 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1372 if (!RC.AltOrderSelect.empty()) { in runTargetDesc()
1373 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1375 << RC.AltOrderSelect << "}\n\n" in runTargetDesc()
1376 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1378 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { in runTargetDesc()
1379 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1388 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" in runTargetDesc()
1391 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) in runTargetDesc()
1392 if (RC.getOrder(oi).empty()) in runTargetDesc()
1396 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1397 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() in runTargetDesc()
1406 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1407 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1409 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " in runTargetDesc()
1410 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " in runTargetDesc()
1411 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; in runTargetDesc()
1412 printMask(OS, RC.LaneMask); in runTargetDesc()
1413 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1414 << (RC.HasDisjunctSubRegs?"true":"false") in runTargetDesc()
1416 << (RC.CoveredBySubRegs?"true":"false") in runTargetDesc()
1418 if (RC.getSuperClasses().empty()) in runTargetDesc()
1421 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1422 if (RC.AltOrderSelect.empty()) in runTargetDesc()
1425 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1434 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1435 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1512 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1513 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1515 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) in runTargetDesc()
1673 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump() local
1674 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1677 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
1680 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; in debugDump()
1681 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; in debugDump()
1682 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; in debugDump()
1683 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1684 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1686 for (const CodeGenRegister *R : RC.getMembers()) { in debugDump()
1691 const BitVector &SubClasses = RC.getSubClasses(); in debugDump()
1699 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { in debugDump()