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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
116 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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H A DAMDGPURegisterBankInfo.cpp100 MachineRegisterInfo &MRI; member in __anon4b888c320111::ApplyRegBankMapping
174 MRI.setRegBank(Reg, *RB); in applyBank()
655 MRI->setRegBank(LoLHS, *Bank); in split64BitValueForMapping()
656 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
672 MRI.setType(Reg, NewTy); in setRegsToType()
1089 LLT Ty = MRI.getType(Reg); in constrainOpWithReadfirstlane()
1103 MRI.setType(SGPR, Ty); in constrainOpWithReadfirstlane()
1268 LLT PtrTy = MRI.getType(Dst); in applyMappingDynStackAlloc()
1423 LLT Ty = MRI.getType(Dst); in applyMappingSBufferLoad()
1801 LLT Ty = MRI.getType(VData); in selectStoreIntrinsic()
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H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
143 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 unsigned getMappingType(const MachineRegisterInfo &MRI,
184 MachineRegisterInfo &MRI,
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H A DGCNRegPressure.cpp75 const auto RC = MRI.getRegClass(Reg); in getRegKind()
98 switch (auto Kind = getRegKind(Reg, MRI)) { in inc()
195 MRI.getMaxLaneMaskForVReg(MO.getReg()) : in getDefRegMask()
258 LiveMask = MRI.getMaxLaneMaskForVReg(Reg); in getLiveLaneMask()
282 MRI = &MF.getRegInfo(); in reset()
300 assert(MRI && "call reset first"); in recede()
328 LiveMask &= ~getDefRegMask(MO, *MRI); in recede()
356 assert(MRI && "call reset first"); in advanceBeforeNext()
403 LiveMask |= getDefRegMask(MO, *MRI); in advanceToNext()
470 printLivesAt(SI, LIS, *MRI); in isValid()
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H A DAMDGPUInstructionSelector.cpp67 MRI = &MF.getRegInfo(); in setupMF()
125 if (isVCC(DstReg, *MRI)) { in selectCOPY()
134 if (!isVCC(SrcReg, *MRI)) { in selectCOPY()
413 if (isVCC(Dst1Reg, *MRI)) { in selectG_UADDO_USUBO_UADDE_USUBE()
1063 if (!isVCC(CCReg, *MRI)) { in selectG_ICMP()
1096 if (isVCC(Dst, *MRI)) in selectIntrinsicIcmp()
1814 if (!isVCC(CCReg, *MRI)) { in selectG_SELECT()
1824 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
2463 MRI->setRegClass( in selectG_AMDGPU_ATOMIC_CMPXCHG()
2841 if (MRI->getType(DstReg) != V2S16 || MRI->getType(Src0Reg) != V2S16) in selectG_SHUFFLE_VECTOR()
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H A DSIFixSGPRCopies.cpp91 MachineRegisterInfo *MRI; member in __anonb3e790490111::SIFixSGPRCopies
143 const MachineRegisterInfo &MRI) { in getCopyRegClasses() argument
199 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
223 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
226 if (!MRI.hasOneUse(DstReg)) in foldVGPRCopyIntoRegSequence()
251 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
408 for (auto &MI : MRI.def_instructions(Reg)) { in hoistAndMergeSGPRInits()
555 MRI.clearKillFlags(Reg); in hoistAndMergeSGPRInits()
567 MRI = &MF.getRegInfo(); in runOnMachineFunction()
841 TRI->getRegClassForReg(*MRI, SrcReg); in processPHINode()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp52 MachineRegisterInfo &MRI) { in IsRegInClass()
94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in __anon783349100111::AArch64AdvSIMDScalar
145 MRI) && in getSrcFromCopy()
149 MRI) && in getSrcFromCopy()
151 MRI)) { in getSrcFromCopy()
208 if (!MRI->def_empty(OrigSrc0)) { in isProfitableToTransform()
210 MRI->def_instr_begin(OrigSrc0); in isProfitableToTransform()
221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform()
223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform()
301 if (!MRI->def_empty(OrigSrc0)) { in transformInstruction()
320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction()
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H A DAArch64Combine.td17 [{ return matchFConstantToConstant(*${root}, MRI); }]),
60 [{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
67 [{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
74 [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
81 [{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
88 [{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
95 [{ return matchEXT(*${root}, MRI, ${matchinfo}); }]),
121 (apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
140 [{ return trySwapICmpOperands(*${root}, MRI); }]),
174 [{ return lowerVectorFCMP(*${root}, MRI, B); }]),
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp358 return selectCopy(I, MRI); in select()
509 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
535 X86SelectAddress(*MRI.getVRegDef(I.getOperand(1).getReg()), MRI, AM); in selectLoadStoreOp()
569 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
622 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
641 LLT Ty = MRI.getType(DefReg); in selectConstant()
814 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI)); in selectZext()
818 DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI)); in selectZext()
909 LLT Ty = MRI.getType(LHS); in selectCmp()
986 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
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H A DX86RegisterBankInfo.cpp148 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameOperandsMapping() local
151 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameOperandsMapping()
154 (Ty != MRI.getType(MI.getOperand(2).getReg()))) in getSameOperandsMapping()
164 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping() local
189 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
215 const LLT Ty0 = MRI.getType(Op0.getReg()); in getInstrMapping()
216 const LLT Ty1 = MRI.getType(Op1.getReg()); in getInstrMapping()
225 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg()); in getInstrMapping()
244 const LLT Ty0 = MRI.getType(Op0.getReg()); in getInstrMapping()
245 const LLT Ty1 = MRI.getType(Op1.getReg()); in getInstrMapping()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp186 if (MRI.getType(DstReg) != MRI.getType(SrcReg)) in canReplaceReg()
191 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg); in canReplaceReg()
370 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantIntVRegVal()
378 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantFPVRegVal()
387 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies()
394 auto SrcTy = MRI.getType(SrcReg); in getDefSrcRegIgnoringCopies()
397 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies()
407 getDefSrcRegIgnoringCopies(Reg, MRI); in getDefIgnoringCopies()
649 MRI.setType(LiveIn, RegTy); in getFunctionLiveInPhysReg()
668 LLT Ty = MRI.getType(Op1); in ConstantFoldExtOp()
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H A DCombinerHelper.cpp2453 if (mi_match(SrcReg, MRI, in matchCombineZextTrunc()
2637 MRI); in matchUndefStore()
2643 MRI); in matchUndefSelectCmp()
2856 if (MRI.hasOneUse(DstReg) && MRI.use_instr_begin(DstReg)->getOpcode() == in matchCombineInsertVecElts()
2933 if (!MRI.hasOneNonDBGUse(LHSReg) || !MRI.hasOneNonDBGUse(RHSReg)) in matchHoistLogicOpWithSameOpcodeHands()
2952 LLT XTy = MRI.getType(X); in matchHoistLogicOpWithSameOpcodeHands()
3063 Dst, MRI, in matchOverlappingAnd()
3429 if (!MRI.hasOneNonDBGUse(OrLHS) || !MRI.hasOneNonDBGUse(OrRHS)) in findCandidatesForLoadOrCombine()
3466 if (!mi_match(Reg, MRI, in matchLoadAndBytePosition()
3969 return isLegalOrBeforeLegalizer({RotateOpc, {MRI.getType(X), MRI.getType(Y)}}); in matchFunnelShiftToRotate()
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h85 Register constrainRegToClass(MachineRegisterInfo &MRI,
100 MachineRegisterInfo &MRI,
119 MachineRegisterInfo &MRI,
202 const MachineRegisterInfo &MRI);
238 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef() argument
239 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); in getOpcodeDef()
252 const MachineRegisterInfo &MRI);
272 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
277 return isKnownNeverNaN(Val, MRI, true); in isKnownNeverSNaN()
352 const MachineRegisterInfo &MRI);
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H A DMIPatternMatch.h25 return P.match(MRI, R); in mi_match()
30 return P.match(MRI, &MI); in mi_match()
39 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
53 return MRI.hasOneNonDBGUse(Reg) && SubPat.match(MRI, Reg); in match()
145 return P.match(MRI, src) && And<Preds...>::match(MRI, src);
163 return P.match(MRI, src) || Or<Preds...>::match(MRI, src);
185 MI = MRI.getVRegDef(Reg);
199 Ty = MRI.getType(Reg);
209 F = getConstantFPVRegVal(Reg, MRI);
486 if (!P.match(MRI, TmpPred))
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H A DLegalizationArtifactCombiner.h33 MachineRegisterInfo &MRI; variable
51 : Builder(B), MRI(MRI), LI(LI) {} in LegalizationArtifactCombiner()
75 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
117 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
122 LLT SrcTy = MRI.getType(SrcReg); in tryCombineZExt()
173 LLT DstTy = MRI.getType(DstReg); in tryCombineSExt()
177 LLT SrcTy = MRI.getType(SrcReg); in tryCombineSExt()
190 if (mi_match(SrcReg, MRI, in tryCombineSExt()
543 MachineRegisterInfo &MRI; variable
758 LLT OpTy = MRI.getType(SrcReg); in tryCombineUnmergeValues()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp647 auto &MRI = MF.getRegInfo(); in getImmedFromMO() local
1110 LLT Ty = MRI.getType(True); in emitSelect()
1175 if (mi_match(Reg, MRI, in emitSelect()
2207 LLT Ty = MRI.getType(X); in earlySelect()
2246 Dst, MRI, in earlySelect()
4375 LLT Ty = MRI.getType(Dst); in emitCSetForFCmp()
4408 LLT Ty = MRI.getType(LHS); in emitFPCompare()
4655 if (isCMN(LHSDef, P, MRI)) in tryFoldIntegerCompare()
4668 if (isCMN(RHSDef, P, MRI)) in tryFoldIntegerCompare()
4912 Dst, *MRI.getRegClass(CPLoad->getOperand(0).getReg()), MRI); in emitConstantVector()
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H A DAArch64PostLegalizerLowering.cpp224 LLT Ty = MRI.getType(Dst); in matchREV()
327 MRI)) in matchDupFromInsertVectorElt()
479 MachineInstr *MI = MRI.getVRegDef(Reg); in isVShiftRImm()
522 const auto &Ty = MRI.getType(RHS); in tryAdjustICmpImmAndPred()
648 const LLT SrcTy = MRI.getType(Src1Reg); in matchDupLane()
750 if (!MRI.hasOneNonDBGUse(CmpOp)) in getCmpOperandFoldingProfit()
859 LLT DstTy = MRI.getType(LHS); in getVectorFCMP()
916 LLT DstTy = MRI.getType(Dst); in lowerVectorFCMP()
927 auto Splat = getAArch64VectorSplat(*MRI.getVRegDef(RHS), MRI); in lowerVectorFCMP()
950 MRI.replaceRegWith(Dst, CmpRes); in lowerVectorFCMP()
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H A DAArch64RegisterBankInfo.cpp520 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints()
536 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyUsesFP()
620 !MRI.getType(DstReg).isValid()) || in getInstrMapping()
622 !MRI.getType(SrcReg).isValid())) { in getInstrMapping()
672 LLT Ty = MRI.getType(MO.getReg()); in getInstrMapping()
690 LLT ScalarTy = MRI.getType(ScalarReg); in getInstrMapping()
695 onlyDefinesFP(*ScalarDef, MRI, TRI))) in getInstrMapping()
763 if (onlyUsesFP(UseMI, MRI, TRI) || onlyDefinesFP(UseMI, MRI, TRI)) { in getInstrMapping()
776 if (onlyDefinesFP(*DefMI, MRI, TRI)) in getInstrMapping()
826 onlyDefinesFP(*DefMI, MRI, TRI)) in getInstrMapping()
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H A DAArch64PostLegalizerCombiner.cpp52 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
56 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchExtractVecEltPairwiseAdd()
77 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd()
80 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd()
113 unsigned Opc = MRI.getVRegDef(R)->getOpcode(); in isSignExtended()
123 MachineInstr &MI, MachineRegisterInfo &MRI, in matchAArch64MulConstCombine() argument
129 const LLT Ty = MRI.getType(LHS); in matchAArch64MulConstCombine()
154 if (MRI.hasOneNonDBGUse(LHS) && in matchAArch64MulConstCombine()
155 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
159 if (MRI.hasOneNonDBGUse(Dst)) { in matchAArch64MulConstCombine()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp100 auto Begin = MRI->use_begin(Op0.getReg()), End = MRI->use_end(); in checkADDrr()
105 if (!MRI->getUniqueVRegDef(I->getReg())) in checkADDrr()
162 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
170 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate()
174 if (!MRI->getUniqueVRegDef(I->getReg())) in processCandidate()
191 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
197 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processDstReg()
205 if (IsAma && MRI->getUniqueVRegDef(I->getReg())) in processDstReg()
206 processInst(MRI, I->getParent(), &*I, GVal); in processDstReg()
235 checkADDrr(MRI, RelocOp, GVal); in processInst()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp48 MachineRegisterInfo &MRI) const;
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
844 auto &MRI = MF.getRegInfo(); in select() local
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1034 return selectSelect(MIB, MRI); in select()
1038 return selectCmp(Helper, MIB, MRI); in select()
1057 return selectCmp(Helper, MIB, MRI); in select()
1077 return selectGlobal(MIB, MRI); in select()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegColoring.cpp65 static float computeWeight(const MachineRegisterInfo *MRI, in computeWeight() argument
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
88 MachineRegisterInfo *MRI = &MF.getRegInfo(); in runOnMachineFunction() local
95 unsigned NumVRegs = MRI->getNumVirtRegs(); in runOnMachineFunction()
105 if (MRI->use_empty(VReg)) in runOnMachineFunction()
110 LI->setWeight(computeWeight(MRI, MBFI, VReg)); in runOnMachineFunction()
121 if (MRI->isLiveIn(LHS->reg()) != MRI->isLiveIn(RHS->reg())) in runOnMachineFunction()
122 return MRI->isLiveIn(LHS->reg()); in runOnMachineFunction()
140 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
143 if (!MRI->isLiveIn(Old)) in runOnMachineFunction()
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H A DWebAssemblyPeephole.cpp62 MachineRegisterInfo &MRI) { in maybeRewriteToDrop() argument
66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
69 MFI.stackifyVReg(MRI, NewReg); in maybeRewriteToDrop()
77 MachineRegisterInfo &MRI, in maybeRewriteToFallthrough() argument
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
123 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
127 MFI.stackifyVReg(MRI, NewReg); in maybeRewriteToFallthrough()
141 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
172 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
175 Changed |= maybeRewriteToDrop(OldReg, NewReg, MO, MFI, MRI); in runOnMachineFunction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp183 assert(!MRI.getType(Reg).isPointer() && in addDefUses()
198 assert(!MRI.getType(Reg).isPointer() && in addUseDef()
200 MachineInstr *DefMI = MRI.getVRegDef(Reg); in addUseDef()
238 addDefUses(MI->getOperand(0).getReg(), MRI); in AmbiguousRegDefUseContainer()
241 addUseDef(MI->getOperand(0).getReg(), MRI); in AmbiguousRegDefUseContainer()
244 addDefUses(MI->getOperand(0).getReg(), MRI); in AmbiguousRegDefUseContainer()
251 addDefUses(MI->getOperand(0).getReg(), MRI); in AmbiguousRegDefUseContainer()
253 addUseDef(MI->getOperand(2).getReg(), MRI); in AmbiguousRegDefUseContainer()
254 addUseDef(MI->getOperand(3).getReg(), MRI); in AmbiguousRegDefUseContainer()
453 LLT RegTy = MRI.getType(Op.getReg()); in getInstrMapping()
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