Lines Matching refs:MRI
91 MachineRegisterInfo *MRI; member in __anonb3e790490111::SIFixSGPRCopies
129 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVectorOperands() local
134 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
143 const MachineRegisterInfo &MRI) { in getCopyRegClasses() argument
148 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
155 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
178 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in tryChangeVGPRtoSGPRinCopy() local
185 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { in tryChangeVGPRtoSGPRinCopy()
199 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
219 MachineRegisterInfo &MRI) { in foldVGPRCopyIntoRegSequence() argument
223 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
226 if (!MRI.hasOneUse(DstReg)) in foldVGPRCopyIntoRegSequence()
229 MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg); in foldVGPRCopyIntoRegSequence()
238 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
251 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
268 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
275 Register TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence()
283 Register TmpAReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence()
394 const MachineRegisterInfo &MRI, in hoistAndMergeSGPRInits() argument
408 for (auto &MI : MRI.def_instructions(Reg)) { in hoistAndMergeSGPRInits()
555 MRI.clearKillFlags(Reg); in hoistAndMergeSGPRInits()
567 MRI = &MF.getRegInfo(); in runOnMachineFunction()
590 std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI); in runOnMachineFunction()
599 = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in runOnMachineFunction()
625 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in runOnMachineFunction()
666 foldVGPRCopyIntoRegSequence(MI, TRI, TII, *MRI); in runOnMachineFunction()
685 DstRC = MRI->getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
686 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
687 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
724 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) && in runOnMachineFunction()
726 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) && in runOnMachineFunction()
736 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); in runOnMachineFunction()
770 hoistAndMergeSGPRInits(AMDGPU::M0, *MRI, TRI, *MDT, TII); in runOnMachineFunction()
787 for (const auto &Use : MRI->use_operands(Reg)) { in processPHINode()
790 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) || in processPHINode()
791 TRI->isAGPR(*MRI, Use.getReg()); in processPHINode()
795 !TRI->isSGPRReg(*MRI, UseMI->getOperand(0).getReg())) { in processPHINode()
805 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg()); in processPHINode()
806 if (!TRI->isSGPRReg(*MRI, Use.getReg()) && in processPHINode()
822 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes); in processPHINode()
825 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
827 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg()); in processPHINode()
836 MachineInstr *Def = MRI->getVRegDef(InputReg); in processPHINode()
837 if (TRI->isVectorRegister(*MRI, InputReg)) { in processPHINode()
841 TRI->getRegClassForReg(*MRI, SrcReg); in processPHINode()
849 TRI->isVectorRegister(*MRI, Def->getOperand(1).getReg())) { in processPHINode()
851 MachineInstr *SrcDef = MRI->getVRegDef(SrcReg); in processPHINode()
869 if ((!TRI->isVectorRegister(*MRI, PHIRes) && in processPHINode()