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Searched refs:DestReg (Results 1 – 25 of 111) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp110 assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) && in emitLoadConstPool()
130 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
141 Register LdReg = DestReg; in emitThumbRegPlusImmInReg()
142 if (DestReg == ARM::SP) in emitThumbRegPlusImmInReg()
144 if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg)) in emitThumbRegPlusImmInReg()
174 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
218 if (DestReg == ARM::SP) { in emitThumbRegPlusImmediate()
230 } else if (isARMLowRegister(DestReg)) { in emitThumbRegPlusImmediate()
237 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
254 if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
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H A DThumb1InstrInfo.cpp41 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
51 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
52 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
62 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
108 Register DestReg, int FI, in loadRegFromStackSlot() argument
113 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
117 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
126 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
H A DThumb2InstrInfo.cpp136 if (!DestReg.isVirtual()) in optimizeSelect()
158 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
208 Register DestReg, int FI, in loadRegFromStackSlot() argument
242 if (Register::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
282 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
294 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
307 .addReg(DestReg) in emitT2RegPlusImmediate()
317 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
329 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
367 bool ToSP = DestReg == ARM::SP; in emitT2RegPlusImmediate()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp91 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
113 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
120 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
123 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
126 Src1Reg = DestReg; in selectSELRMux()
130 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
133 Src2Reg = DestReg; in selectSELRMux()
139 if (DestReg != Src1Reg && DestReg == Src2Reg) { in selectSELRMux()
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H A DSystemZInstrInfo.cpp154 Register DestReg = MI.getOperand(0).getReg(); in expandRIEPseudo() local
156 bool DestIsHigh = SystemZ::isHighReg(DestReg); in expandRIEPseudo()
161 if (DestReg != SrcReg) { in expandRIEPseudo()
165 MI.getOperand(1).setReg(DestReg); in expandRIEPseudo()
253 bool DestIsHigh = SystemZ::isHighReg(DestReg); in emitGRX32Move()
266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
267 .addReg(DestReg, RegState::Undef) in emitGRX32Move()
796 if (SystemZ::VR128BitRegClass.contains(DestReg) && in copyPhysReg()
810 if (SystemZ::FP128BitRegClass.contains(DestReg) && in copyPhysReg()
827 if (DestReg == SystemZ::CC) { in copyPhysReg()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
359 } else if (SP::ASRRegsRegClass.contains(DestReg) && in copyPhysReg()
361 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) in copyPhysReg()
364 } else if (SP::IntRegsRegClass.contains(DestReg) && in copyPhysReg()
366 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) in copyPhysReg()
378 Register Dst = TRI->getSubReg(DestReg, subRegIdx[i]); in copyPhysReg()
389 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysReg()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp425 if (Opnd.getReg() == DestReg) { in searchALUInst()
580 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
597 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
599 if (DestReg != BaseReg) in optTwoAddrLEA()
768 Register DestReg = Dest.getReg(); in processInstrForSlow3OpLEA() local
797 if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) { in processInstrForSlow3OpLEA()
799 if (DestReg != BaseReg) in processInstrForSlow3OpLEA()
839 .addReg(DestReg); in processInstrForSlow3OpLEA()
844 .addReg(DestReg) in processInstrForSlow3OpLEA()
872 .addReg(DestReg) in processInstrForSlow3OpLEA()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp221 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
240 .addReg(DestReg) in doAtomicBinOpExpansion()
283 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
311 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
316 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
321 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
422 Register DestReg = MI.getOperand(0).getReg(); in expandAtomicMinMaxOp() local
442 .addReg(DestReg) in expandAtomicMinMaxOp()
445 .addReg(DestReg) in expandAtomicMinMaxOp()
550 .addReg(DestReg) in expandAtomicCmpXchg()
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H A DRISCVMergeBaseOffset.cpp181 Register DestReg = LoADDI.getOperand(0).getReg(); in detectAndFoldOffset() local
182 assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI"); in detectAndFoldOffset()
184 MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent(); in detectAndFoldOffset()
207 if (!matchLargeOffset(Tail, DestReg, Offset)) in detectAndFoldOffset()
238 if (DestReg != BaseAddrReg) in detectAndFoldOffset()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp397 return DestReg; in materializeFP()
405 return DestReg; in materializeFP()
421 emitInst(Mips::LW, DestReg) in materializeGV()
428 .addReg(DestReg) in materializeGV()
430 DestReg = TempReg; in materializeGV()
432 return DestReg; in materializeGV()
438 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
441 return DestReg; in materializeExternalCallSym()
1087 if (!DestReg) in selectFPTrunc()
1601 if (DestReg == 0) in fastLowerIntrinsicCall()
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H A DMipsSEInstrInfo.cpp124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
138 .addReg(DestReg) in copyPhysReg()
161 Opc = Mips::MTHI64, DestReg = 0; in copyPhysReg()
163 Opc = Mips::MTLO64, DestReg = 0; in copyPhysReg()
176 if (DestReg) in copyPhysReg()
177 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
329 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || in loadRegFromStack()
330 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); in loadRegFromStack()
384 if (DestReg == Mips::HI0) in loadRegFromStack()
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H A DMips16InstrInfo.cpp71 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
75 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
82 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
85 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
92 if (DestReg) in copyPhysReg()
93 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
126 Register DestReg, int FI, in loadRegFromStack() argument
138 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) in loadRegFromStack()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp268 Register DestReg = MI->getOperand(0).getReg(); in getAluKind() local
269 if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || in getAluKind()
270 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind()
272 if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) in getAluKind()
274 if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) in getAluKind()
276 if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) in getAluKind()
278 if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) in getAluKind()
355 Register DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
362 MO.getReg() == DestReg) in AssignSlot()
368 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
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H A DAMDGPUMachineCFGStructurizer.cpp43 unsigned DestReg;
67 void deleteDef(unsigned DestReg);
73 unsigned &DestReg);
112 return Info->DestReg; in phiInfoElementGetDest()
117 Info->DestReg = NewDef; in phiInfoElementSetDef()
200 NewElement->DestReg = DestReg; in addDest()
238 unsigned DestReg; in isSource() local
2062 unsigned DestReg; in rewriteLiveOutRegs() local
2080 unsigned DestReg = *DRI; in prunePHIInfo() local
2199 unsigned DestReg = *DRI; in createEntryPHIs() local
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp79 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
82 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) in runOnMachineFunction()
86 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp33 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
149 Register DestReg, int FI, in loadRegFromStackSlot() argument
157 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
159 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h336 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
338 .addReg(DestReg, RegState::Define); in BuildMI()
347 Register DestReg) { in BuildMI() argument
351 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
363 Register DestReg) { in BuildMI() argument
367 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
372 Register DestReg) { in BuildMI() argument
377 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg); in BuildMI()
382 Register DestReg) { in BuildMI() argument
383 return BuildMI(BB, *I, DL, MCID, DestReg); in BuildMI()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp43 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
50 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
51 if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
57 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
67 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
69 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { in copyPhysReg()
71 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { in copyPhysReg()
77 BuildMI(MBB, MI, DL, get(Opc), DestReg) in copyPhysReg()
161 Register DestReg, int FrameIndex, in loadRegFromStackSlot() argument
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp614 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
619 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
620 ActiveChains[DestReg] = G.get(); in scanInstruction()
627 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
632 if (DestReg != AccumReg) in scanInstruction()
647 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
649 if (DestReg != AccumReg) { in scanInstruction()
650 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
663 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
664 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
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H A DAArch64InstrInfo.cpp3511 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub, in copyPhysReg()
3528 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub, in copyPhysReg()
3545 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
3553 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
3566 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
3574 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
3795 Register DestReg0 = DestReg; in loadRegPairFromStackSlot()
4040 Register TmpReg = DestReg; in emitFrameOffsetAdj()
4056 TmpReg = DestReg; in emitFrameOffsetAdj()
4117 SrcReg = DestReg; in emitFrameOffset()
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H A DAArch64AsmPrinter.cpp890 Register DestReg = MI.getOperand(0).getReg(); in LowerJumpTableDest() local
914 .addReg(DestReg) in LowerJumpTableDest()
937 .addReg(DestReg) in LowerJumpTableDest()
938 .addReg(DestReg) in LowerJumpTableDest()
1096 Register DestReg = MI.getOperand(0).getReg(); in emitFMov0() local
1099 if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31) in emitFMov0()
1100 DestReg = AArch64::D0 + (DestReg - AArch64::H0); in emitFMov0()
1101 else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) in emitFMov0()
1102 DestReg = AArch64::D0 + (DestReg - AArch64::S0); in emitFMov0()
1104 assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31); in emitFMov0()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp65 Register DestReg, int FrameIdx, in loadRegFromStackSlot() argument
80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
92 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
95 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
97 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
102 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp354 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysSubRegs()
364 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { in copyPhysReg()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
368 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
387 } else if (VE::VMRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
406 << " to " << printReg(DestReg, TRI) << "\n"; in copyPhysReg()
519 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg) in loadRegFromStackSlot()
525 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg) in loadRegFromStackSlot()
531 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) in loadRegFromStackSlot()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp59 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
65 Register::isVirtualRegister(DestReg) in copyPhysReg()
66 ? MRI.getRegClass(DestReg) in copyPhysReg()
67 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
87 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) in copyPhysReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp986 unsigned DestReg; in SelectFPTrunc() local
1001 TII.get(PPC::FRSP), DestReg) in SelectFPTrunc()
1005 updateValueMap(I, DestReg); in SelectFPTrunc()
1097 updateValueMap(I, DestReg); in SelectIToFP()
1142 updateValueMap(I, DestReg); in SelectIToFP()
1222 unsigned DestReg; in SelectFPToI() local
1255 ? DestReg in SelectFPToI()
1837 DestReg) in PPCEmitIntExt()
2058 return DestReg; in PPCMaterializeFP()
2089 DestReg) in PPCMaterializeGV()
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