Lines Matching refs:DestReg
3223 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, in forwardCopyWillClobberTuple() argument
3227 return ((DestReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
3232 const DebugLoc &DL, MCRegister DestReg, in copyPhysRegTuple() argument
3238 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyPhysRegTuple()
3251 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
3259 DebugLoc DL, unsigned DestReg, in copyGPRRegTuple() argument
3267 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyGPRRegTuple()
3275 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyGPRRegTuple()
3284 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
3286 if (AArch64::GPR32spRegClass.contains(DestReg) && in copyPhysReg()
3290 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { in copyPhysReg()
3295 DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass); in copyPhysReg()
3308 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg) in copyPhysReg()
3314 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg) in copyPhysReg()
3321 DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass); in copyPhysReg()
3334 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg) in copyPhysReg()
3343 if (AArch64::PPRRegClass.contains(DestReg) && in copyPhysReg()
3346 BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg) in copyPhysReg()
3354 if (AArch64::ZPRRegClass.contains(DestReg) && in copyPhysReg()
3357 BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ), DestReg) in copyPhysReg()
3364 if (AArch64::ZPR2RegClass.contains(DestReg) && in copyPhysReg()
3367 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORR_ZZZ, in copyPhysReg()
3373 if (AArch64::ZPR3RegClass.contains(DestReg) && in copyPhysReg()
3377 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORR_ZZZ, in copyPhysReg()
3383 if (AArch64::ZPR4RegClass.contains(DestReg) && in copyPhysReg()
3387 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORR_ZZZ, in copyPhysReg()
3392 if (AArch64::GPR64spRegClass.contains(DestReg) && in copyPhysReg()
3394 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) { in copyPhysReg()
3396 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg) in copyPhysReg()
3401 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg) in copyPhysReg()
3406 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg) in copyPhysReg()
3414 if (AArch64::DDDDRegClass.contains(DestReg) && in copyPhysReg()
3418 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
3424 if (AArch64::DDDRegClass.contains(DestReg) && in copyPhysReg()
3428 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
3434 if (AArch64::DDRegClass.contains(DestReg) && in copyPhysReg()
3437 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
3443 if (AArch64::QQQQRegClass.contains(DestReg) && in copyPhysReg()
3447 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
3453 if (AArch64::QQQRegClass.contains(DestReg) && in copyPhysReg()
3457 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
3463 if (AArch64::QQRegClass.contains(DestReg) && in copyPhysReg()
3466 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
3471 if (AArch64::XSeqPairsClassRegClass.contains(DestReg) && in copyPhysReg()
3474 copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRXrs, in copyPhysReg()
3479 if (AArch64::WSeqPairsClassRegClass.contains(DestReg) && in copyPhysReg()
3482 copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRWrs, in copyPhysReg()
3487 if (AArch64::FPR128RegClass.contains(DestReg) && in copyPhysReg()
3490 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
3501 .addReg(DestReg, RegState::Define) in copyPhysReg()
3508 if (AArch64::FPR64RegClass.contains(DestReg) && in copyPhysReg()
3511 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub, in copyPhysReg()
3515 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
3519 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg) in copyPhysReg()
3525 if (AArch64::FPR32RegClass.contains(DestReg) && in copyPhysReg()
3528 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub, in copyPhysReg()
3532 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
3536 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
3542 if (AArch64::FPR16RegClass.contains(DestReg) && in copyPhysReg()
3545 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
3549 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
3553 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
3557 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
3563 if (AArch64::FPR8RegClass.contains(DestReg) && in copyPhysReg()
3566 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
3570 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
3574 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
3578 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
3585 if (AArch64::FPR64RegClass.contains(DestReg) && in copyPhysReg()
3587 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg) in copyPhysReg()
3591 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()
3593 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg) in copyPhysReg()
3598 if (AArch64::FPR32RegClass.contains(DestReg) && in copyPhysReg()
3600 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg) in copyPhysReg()
3604 if (AArch64::GPR32RegClass.contains(DestReg) && in copyPhysReg()
3606 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg) in copyPhysReg()
3611 if (DestReg == AArch64::NZCV) { in copyPhysReg()
3621 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); in copyPhysReg()
3622 BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg) in copyPhysReg()
3630 errs() << TRI.getRegAsmName(DestReg) << " = COPY " in copyPhysReg()
3792 Register DestReg, unsigned SubIdx0, in loadRegPairFromStackSlot() argument
3795 Register DestReg0 = DestReg; in loadRegPairFromStackSlot()
3796 Register DestReg1 = DestReg; in loadRegPairFromStackSlot()
3798 if (Register::isPhysicalRegister(DestReg)) { in loadRegPairFromStackSlot()
3799 DestReg0 = TRI.getSubReg(DestReg, SubIdx0); in loadRegPairFromStackSlot()
3801 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3814 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, in loadRegFromStackSlot() argument
3844 if (Register::isVirtualRegister(DestReg)) in loadRegFromStackSlot()
3845 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
3847 assert(DestReg != AArch64::WSP); in loadRegFromStackSlot()
3854 if (Register::isVirtualRegister(DestReg)) in loadRegFromStackSlot()
3855 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
3857 assert(DestReg != AArch64::SP); in loadRegFromStackSlot()
3862 get(AArch64::LDPWi), DestReg, AArch64::sube32, in loadRegFromStackSlot()
3876 get(AArch64::LDPXi), DestReg, AArch64::sube64, in loadRegFromStackSlot()
3935 .addReg(DestReg, getDefRegState(true)) in loadRegFromStackSlot()
3999 const DebugLoc &DL, unsigned DestReg, in emitFrameOffsetAdj() argument
4040 Register TmpReg = DestReg; in emitFrameOffsetAdj()
4056 TmpReg = DestReg; in emitFrameOffsetAdj()
4068 if ((DestReg == AArch64::FP && SrcReg == AArch64::SP) || in emitFrameOffsetAdj()
4069 (SrcReg == AArch64::FP && DestReg == AArch64::SP)) { in emitFrameOffsetAdj()
4080 } else if (DestReg == AArch64::SP) { in emitFrameOffsetAdj()
4098 unsigned DestReg, unsigned SrcReg, in emitFrameOffset() argument
4107 if (Bytes || (!Offset && SrcReg != DestReg)) { in emitFrameOffset()
4108 assert((DestReg != AArch64::SP || Bytes % 8 == 0) && in emitFrameOffset()
4115 emitFrameOffsetAdj(MBB, MBBI, DL, DestReg, SrcReg, Bytes, Opc, TII, Flag, in emitFrameOffset()
4117 SrcReg = DestReg; in emitFrameOffset()
4126 emitFrameOffsetAdj(MBB, MBBI, DL, DestReg, SrcReg, NumDataVectors, in emitFrameOffset()
4128 SrcReg = DestReg; in emitFrameOffset()
4132 assert(DestReg != AArch64::SP && "Unaligned access to SP"); in emitFrameOffset()
4133 emitFrameOffsetAdj(MBB, MBBI, DL, DestReg, SrcReg, NumPredicateVectors, in emitFrameOffset()
7516 Register DestReg = DestSrc->Destination->getReg(); in describeORRLoadedValue() local
7522 if (DestReg == DescribedReg) in describeORRLoadedValue()
7527 TRI->isSuperRegister(DestReg, DescribedReg)) in describeORRLoadedValue()
7532 TRI->isSubRegister(DestReg, DescribedReg)) { in describeORRLoadedValue()
7537 assert(!TRI->isSuperOrSubRegisterEq(DestReg, DescribedReg) && in describeORRLoadedValue()