413   Register DestReg = I->getOperand(0).getReg();  in searchALUInst()  local
425         if (Opnd.getReg() == DestReg) {  in searchALUInst()
446         if (TRI->regsOverlap(DestReg, Opnd.getReg()))  in searchALUInst()
575   Register DestReg = MI.getOperand(0).getReg();  in optTwoAddrLEA()  local
580   if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))  in optTwoAddrLEA()
597       (DestReg == BaseReg || DestReg == IndexReg)) {  in optTwoAddrLEA()
599     if (DestReg != BaseReg)  in optTwoAddrLEA()
604       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
609       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
612   } else if (DestReg == BaseReg && IndexReg == 0) {  in optTwoAddrLEA()
626         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
629         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
636         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
640         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
768   Register DestReg = Dest.getReg();  in processInstrForSlow3OpLEA()  local
785   if (IsInefficientBase && DestReg == BaseReg && !IsScale1)  in processInstrForSlow3OpLEA()
797   if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {  in processInstrForSlow3OpLEA()
799     if (DestReg != BaseReg)  in processInstrForSlow3OpLEA()
804       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
810       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
838         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
839                     .addReg(DestReg);  in processInstrForSlow3OpLEA()
843         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
844                     .addReg(DestReg)  in processInstrForSlow3OpLEA()
857   assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");  in processInstrForSlow3OpLEA()
867     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);  in processInstrForSlow3OpLEA()
871     NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
872                 .addReg(DestReg)  in processInstrForSlow3OpLEA()
894   NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
895               .addReg(DestReg)  in processInstrForSlow3OpLEA()