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Searched refs:CSR_WRITE_2 (Results 1 – 25 of 41) sorted by relevance

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/freebsd-13.1/sys/dev/xl/
H A Dif_xl.c411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); in xl_mii_bitbang_write()
576 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
579 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
2130 CSR_WRITE_2(sc, XL_COMMAND, in xl_txeoc()
2133 CSR_WRITE_2(sc, XL_COMMAND, in xl_txeoc()
2170 CSR_WRITE_2(sc, XL_COMMAND, in xl_intr()
2256 CSR_WRITE_2(sc, XL_COMMAND, in xl_poll_locked()
2713 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); in xl_init_locked()
2774 CSR_WRITE_2(sc, XL_COMMAND, in xl_init_locked()
3062 CSR_WRITE_2(sc, XL_COMMAND, in xl_ioctl()
[all …]
H A Dif_xlreg.h656 #define CSR_WRITE_2(sc, reg, val) \ macro
674 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x); \
/freebsd-13.1/sys/dev/vte/
H A Dif_vte.c204 CSR_WRITE_2(sc, VTE_MMWD, val); in vte_miibus_writereg()
261 CSR_WRITE_2(sc, VTE_MRICR, val); in vte_miibus_statchg()
269 CSR_WRITE_2(sc, VTE_MTICR, val); in vte_miibus_statchg()
1259 CSR_WRITE_2(sc, VTE_MCR0, mcr); in vte_mac_config()
1360 CSR_WRITE_2(sc, VTE_MIER, 0); in vte_intr()
1626 CSR_WRITE_2(sc, VTE_MACSM, 0); in vte_reset()
1742 CSR_WRITE_2(sc, VTE_MRICR, 0); in vte_init_locked()
1743 CSR_WRITE_2(sc, VTE_MTICR, 0); in vte_init_locked()
1752 CSR_WRITE_2(sc, VTE_MISR, 0); in vte_init_locked()
1783 CSR_WRITE_2(sc, VTE_MIER, 0); in vte_stop()
[all …]
H A Dif_vtevar.h151 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-13.1/sys/dev/bwi/
H A Dbwimac.c219 CSR_WRITE_2(sc, data_reg, v); in bwi_memobj_write_2()
368 CSR_WRITE_2(sc, 0x60e, 0); in bwi_mac_init()
370 CSR_WRITE_2(sc, 0x604, 0); in bwi_mac_init()
722 CSR_WRITE_2(sc, 0x568, 0); in bwi_mac_dummy_xmit()
723 CSR_WRITE_2(sc, 0x7c0, 0); in bwi_mac_dummy_xmit()
725 CSR_WRITE_2(sc, 0x508, 0); in bwi_mac_dummy_xmit()
726 CSR_WRITE_2(sc, 0x50a, 0); in bwi_mac_dummy_xmit()
727 CSR_WRITE_2(sc, 0x54c, 0); in bwi_mac_dummy_xmit()
728 CSR_WRITE_2(sc, 0x56a, 0x14); in bwi_mac_dummy_xmit()
730 CSR_WRITE_2(sc, 0x500, 0); in bwi_mac_dummy_xmit()
[all …]
H A Dbwiphy.c141 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); in bwi_phy_write()
142 CSR_WRITE_2(sc, BWI_PHY_DATA, data); in bwi_phy_write()
150 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); in bwi_phy_read()
443 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT); in bwi_phy_init_11b_rev4()
453 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1); in bwi_phy_init_11b_rev4()
490 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100); in bwi_phy_init_11b_rev4()
537 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0); in bwi_phy_init_11b_rev5()
561 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT); in bwi_phy_init_11b_rev5()
569 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1); in bwi_phy_init_11b_rev5()
730 CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2); in bwi_phy_init_11b_rev6()
[all …]
H A Dbwirf.c203 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); in bwi_rf_write()
204 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data); in bwi_rf_write()
222 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); in bwi_rf_read()
788 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f); in bwi_rf_init_bcm2050()
826 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122); in bwi_rf_init_bcm2050()
1313 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0); in bwi_rf_lo_update_11g()
1376 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div); in bwi_rf_lo_update_11g()
1677 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f); in bwi_rf_calc_nrssi_slope_11b()
1691 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40); in bwi_rf_calc_nrssi_slope_11b()
1693 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122); in bwi_rf_calc_nrssi_slope_11b()
[all …]
H A Dif_bwivar.h84 #define CSR_WRITE_2(sc, reg, val) \ macro
90 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
95 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
100 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
/freebsd-13.1/sys/dev/an/
H A Dif_an.c345 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0); in an_probe()
1517 CSR_WRITE_2(sc, AN_DATA1, len); in an_write_record()
1522 CSR_WRITE_2(sc, AN_DATA1, *ptr++); in an_write_record()
1652 CSR_WRITE_2(sc, selreg, id); in an_seek()
1653 CSR_WRITE_2(sc, offreg, off); in an_seek()
1703 CSR_WRITE_2(sc, AN_DATA0, *ptr++); in an_write_data()
1742 CSR_WRITE_2(sc, AN_DATA0, 0); in an_alloc_nicmem()
3616 CSR_WRITE_2(sc, AN_SW1(sc->mpi350), 0); in flashgchar()
3671 CSR_WRITE_2(sc, AN_SW1(sc->mpi350), 0); in flashpchar()
3693 CSR_WRITE_2(sc, AN_AUX_PAGE, 0x100); in flashputbuf()
[all …]
/freebsd-13.1/sys/dev/ste/
H A Dif_ste.c300 CSR_WRITE_2(sc, STE_MACCTL0, cfg); in ste_miibus_statchg()
556 CSR_WRITE_2(sc, STE_COUNTDOWN, in ste_intr()
583 CSR_WRITE_2(sc, STE_IMR, intrs); in ste_intr()
1527 CSR_WRITE_2(sc, STE_PAR0 + i, in ste_init_locked()
1590 CSR_WRITE_2(sc, STE_MACCTL0, 0); in ste_init_locked()
1591 CSR_WRITE_2(sc, STE_MACCTL1, 0); in ste_init_locked()
1600 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); in ste_init_locked()
1601 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); in ste_init_locked()
1605 CSR_WRITE_2(sc, STE_IMR, 0); in ste_init_locked()
1637 CSR_WRITE_2(sc, STE_IMR, 0); in ste_stop()
[all …]
/freebsd-13.1/sys/dev/stge/
H A Dif_stge.c403 CSR_WRITE_2(sc, STGE_EepromCtrl, in stge_read_eeprom()
1317 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_ioctl()
1325 CSR_WRITE_2(sc, STGE_IntEnable, in stge_ioctl()
2096 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_init_locked()
2135 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init_locked()
2139 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init_locked()
2142 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init_locked()
2223 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_stop()
2507 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); in stge_set_filter()
2542 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); in stge_set_multi()
[all …]
/freebsd-13.1/sys/dev/vge/
H A Dif_vgevar.h221 #define CSR_WRITE_2(sc, reg, val) \ macro
236 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
243 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
H A Dif_vge.c409 CSR_WRITE_2(sc, VGE_MIIDATA, data); in vge_miibus_writereg()
1602 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, in vge_rxeof()
2010 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); in vge_start_locked()
2092 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); in vge_init_locked()
2096 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); in vge_init_locked()
2097 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); in vge_init_locked()
2107 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); in vge_init_locked()
2117 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); in vge_init_locked()
2419 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); in vge_stop()
/freebsd-13.1/sys/dev/vr/
H A Dif_vr.c276 CSR_WRITE_2(sc, VR_MIIDATA, data); in vr_miibus_writereg()
744 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); in vr_attach()
745 CSR_WRITE_2(sc, VR_IMR, 0); in vr_attach()
747 CSR_WRITE_2(sc, VR_MII_IMR, 0); in vr_attach()
1687 CSR_WRITE_2(sc, VR_IMR, 0x0000); in vr_intr()
1718 CSR_WRITE_2(sc, VR_IMR, 0); in vr_int_task()
1766 CSR_WRITE_2(sc, VR_IMR, 0); in vr_error()
2153 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); in vr_init_locked()
2159 CSR_WRITE_2(sc, VR_IMR, 0); in vr_init_locked()
2167 CSR_WRITE_2(sc, VR_MII_IMR, 0); in vr_init_locked()
[all …]
H A Dif_vrreg.h752 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val) macro
761 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
762 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-13.1/sys/dev/rl/
H A Dif_rl.c470 CSR_WRITE_2(sc, rl8139_reg, data); in rl_miibus_writereg()
1218 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); in rl_rxeof()
1475 CSR_WRITE_2(sc, RL_ISR, status); in rl_poll_locked()
1514 CSR_WRITE_2(sc, RL_IMR, 0); in rl_intr()
1516 CSR_WRITE_2(sc, RL_ISR, status); in rl_intr()
1540 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_intr()
1751 CSR_WRITE_2(sc, RL_IMR, 0); in rl_init_locked()
1755 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_init_locked()
1857 CSR_WRITE_2(sc, RL_IMR, 0x0000); in rl_ioctl()
1868 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_ioctl()
[all …]
H A Dif_rlreg.h950 #define CSR_WRITE_2(sc, reg, val) \ macro
972 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/freebsd-13.1/sys/dev/re/
H A Dif_re.c613 CSR_WRITE_2(sc, re8139_reg, data); in re_miibus_writereg()
840 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); in re_diag()
852 CSR_WRITE_2(sc, RL_ISR, status); in re_diag()
2571 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr()
2666 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr_msi()
2724 CSR_WRITE_2(sc, RL_IMR, intrs); in re_intr_msi()
3182 CSR_WRITE_2(sc, 0xe2, 0); in re_init_locked()
3272 CSR_WRITE_2(sc, RL_IMR, 0); in re_init_locked()
3280 CSR_WRITE_2(sc, RL_IMR, 0); in re_init_locked()
3663 CSR_WRITE_2(sc, RL_IMR, 0x0000); in re_stop()
[all …]
/freebsd-13.1/sys/dev/msk/
H A Dif_msk.c691 CSR_WRITE_2(sc_if->msk_softc, in msk_rx_fill()
756 CSR_WRITE_2(sc_if->msk_softc, in msk_init_rx_ring()
824 CSR_WRITE_2(sc_if->msk_softc, in msk_init_jumbo_rx_ring()
1380 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_reset()
1381 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); in mskc_reset()
1391 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); in mskc_reset()
1786 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); in mskc_attach()
2096 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_detach()
2956 CSR_WRITE_2(sc_if->msk_softc, in msk_start_locked()
3010 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_shutdown()
[all …]
/freebsd-13.1/sys/dev/fxp/
H A Dif_fxp.c1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
1170 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_getword()
1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1188 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1207 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1210 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_getword()
1227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
1236 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
1248 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
[all …]
H A Dif_fxpvar.h250 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) macro
/freebsd-13.1/sys/dev/ipw/
H A Dif_ipwreg.h339 #define CSR_WRITE_2(sc, reg, val) \ macro
367 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/freebsd-13.1/sys/dev/iwi/
H A Dif_iwireg.h589 #define CSR_WRITE_2(sc, reg, val) \ macro
609 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/freebsd-13.1/sys/dev/ale/
H A Dif_alevar.h233 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-13.1/sys/dev/sk/
H A Dif_sk.c428 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
430 CSR_WRITE_2(sc, reg, val);
1220 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1221 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1223 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1226 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1228 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1230 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1786 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
2579 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);

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