193 	CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
196 	CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
300 		CSR_WRITE_2(sc, STE_MACCTL0, cfg);  in ste_miibus_statchg()
397 		CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));  in ste_read_eeprom()
452 	CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);  in ste_rxfilter()
453 	CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);  in ste_rxfilter()
454 	CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);  in ste_rxfilter()
455 	CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);  in ste_rxfilter()
556 				CSR_WRITE_2(sc, STE_COUNTDOWN,  in ste_intr()
583 		CSR_WRITE_2(sc, STE_IMR, intrs);  in ste_intr()
731 		CSR_WRITE_2(sc, STE_TX_STATUS, txstat);  in ste_txeoc()
1527 		CSR_WRITE_2(sc, STE_PAR0 + i,  in ste_init_locked()
1556 	CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);  in ste_init_locked()
1562 	CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);  in ste_init_locked()
1590 	CSR_WRITE_2(sc, STE_MACCTL0, 0);  in ste_init_locked()
1591 	CSR_WRITE_2(sc, STE_MACCTL1, 0);  in ste_init_locked()
1600 	CSR_WRITE_2(sc, STE_COUNTDOWN, 0);  in ste_init_locked()
1601 	CSR_WRITE_2(sc, STE_ISR, 0xFFFF);  in ste_init_locked()
1605 		CSR_WRITE_2(sc, STE_IMR, 0);  in ste_init_locked()
1609 	CSR_WRITE_2(sc, STE_IMR, STE_INTRS);  in ste_init_locked()
1637 	CSR_WRITE_2(sc, STE_IMR, 0);  in ste_stop()
1638 	CSR_WRITE_2(sc, STE_COUNTDOWN, 0);  in ste_stop()
1654 	CSR_WRITE_2(sc, STE_MACCTL1, val);  in ste_stop()
1731 		CSR_WRITE_2(sc, STE_MACCTL1, mac);  in ste_restart_tx()
1794 				CSR_WRITE_2(sc, STE_IMR, 0);  in ste_ioctl()
1798 				CSR_WRITE_2(sc, STE_IMR, STE_INTRS);  in ste_ioctl()