180 	CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |  in vte_miibus_readreg()
204 	CSR_WRITE_2(sc, VTE_MMWD, val);  in vte_miibus_writereg()
205 	CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |  in vte_miibus_writereg()
261 		CSR_WRITE_2(sc, VTE_MRICR, val);  in vte_miibus_statchg()
269 		CSR_WRITE_2(sc, VTE_MTICR, val);  in vte_miibus_statchg()
1163 		CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);  in vte_start_locked()
1259 	CSR_WRITE_2(sc, VTE_MCR0, mcr);  in vte_mac_config()
1360 	CSR_WRITE_2(sc, VTE_MIER, 0);  in vte_intr()
1381 		CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);  in vte_intr()
1580 		CSR_WRITE_2(sc, VTE_MRDCR, prog |  in vte_rxeof()
1612 	CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);  in vte_reset()
1625 	CSR_WRITE_2(sc, VTE_MACSM, 0x0002);  in vte_reset()
1626 	CSR_WRITE_2(sc, VTE_MACSM, 0);  in vte_reset()
1683 	CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);  in vte_init_locked()
1684 	CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);  in vte_init_locked()
1685 	CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);  in vte_init_locked()
1689 	CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);  in vte_init_locked()
1690 	CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);  in vte_init_locked()
1693 	CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);  in vte_init_locked()
1694 	CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);  in vte_init_locked()
1701 	CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |  in vte_init_locked()
1714 	CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);  in vte_init_locked()
1717 	CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |  in vte_init_locked()
1728 	CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);  in vte_init_locked()
1735 	CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |  in vte_init_locked()
1742 	CSR_WRITE_2(sc, VTE_MRICR, 0);  in vte_init_locked()
1743 	CSR_WRITE_2(sc, VTE_MTICR, 0);  in vte_init_locked()
1746 	CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);  in vte_init_locked()
1751 	CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);  in vte_init_locked()
1752 	CSR_WRITE_2(sc, VTE_MISR, 0);  in vte_init_locked()
1783 	CSR_WRITE_2(sc, VTE_MIER, 0);  in vte_stop()
1784 	CSR_WRITE_2(sc, VTE_MECIER, 0);  in vte_stop()
1838 		CSR_WRITE_2(sc, VTE_MCR0, mcr);  in vte_start_mac()
1864 		CSR_WRITE_2(sc, VTE_MCR0, mcr);  in vte_stop_mac()
2036 	CSR_WRITE_2(sc, VTE_MAR0, ctx.mchash[0]);  in vte_rxfilter()
2037 	CSR_WRITE_2(sc, VTE_MAR1, ctx.mchash[1]);  in vte_rxfilter()
2038 	CSR_WRITE_2(sc, VTE_MAR2, ctx.mchash[2]);  in vte_rxfilter()
2039 	CSR_WRITE_2(sc, VTE_MAR3, ctx.mchash[3]);  in vte_rxfilter()
2042 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,  in vte_rxfilter()
2044 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,  in vte_rxfilter()
2046 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,  in vte_rxfilter()
2049 	CSR_WRITE_2(sc, VTE_MCR0, mcr);  in vte_rxfilter()