691 		CSR_WRITE_2(sc_if->msk_softc,  in msk_rx_fill()
756 	CSR_WRITE_2(sc_if->msk_softc,  in msk_init_rx_ring()
824 	CSR_WRITE_2(sc_if->msk_softc,  in msk_init_jumbo_rx_ring()
1298 			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);  in msk_phy_power()
1312 			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),  in msk_phy_power()
1314 			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),  in msk_phy_power()
1371 			CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);  in mskc_reset()
1375 		CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);  in mskc_reset()
1380 		CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);  in mskc_reset()
1381 		CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);  in mskc_reset()
1391 	CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);  in mskc_reset()
1446 	CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);  in mskc_reset()
1470 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);  in mskc_reset()
1471 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);  in mskc_reset()
1539 	CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1);  in mskc_reset()
1543 		CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);  in mskc_reset()
1548 		CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);  in mskc_reset()
1786 	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);  in mskc_attach()
2093 	CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);  in mskc_detach()
2096 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);  in mskc_detach()
2956 		CSR_WRITE_2(sc_if->msk_softc,  in msk_start_locked()
3010 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);  in mskc_shutdown()
3040 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);  in mskc_suspend()
3452 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),  in msk_handle_hwerr()
3459 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),  in msk_handle_hwerr()
3581 	CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,  in msk_rxput()
3922 	CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);  in msk_init_locked()
3934 		CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),  in msk_init_locked()
3936 		CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),  in msk_init_locked()
3969 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);  in msk_init_locked()
3974 			CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),  in msk_init_locked()
3993 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);  in msk_init_locked()
4135 	CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),  in msk_set_prefetch()