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Searched refs:hasSubClassEq (Results 1 – 25 of 30) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp260 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
289 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
291 else if (Mips::LO64RegClass.hasSubClassEq(RC)) in storeRegToStack()
293 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in storeRegToStack()
295 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in storeRegToStack()
297 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) in storeRegToStack()
304 if (Mips::HI32RegClass.hasSubClassEq(RC)) { in storeRegToStack()
338 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
367 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
369 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
[all …]
H A DMips16InstrInfo.cpp121 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
140 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp47 if (X86::GR8RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
48 X86::GR16RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
49 X86::GR32RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
50 X86::GR64RegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
53 if (X86::FR32XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
54 X86::FR64XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
55 X86::VR128XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
56 X86::VR256XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
57 X86::VR512RegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
H A DX86DomainReassignment.cpp46 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
49 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
54 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
70 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
72 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
74 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
76 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
H A DX86InstrInfo.cpp2894 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
2895 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
2896 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
3123 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3128 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3130 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3134 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3142 if (X86::GR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3144 if (X86::FR64XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3148 if (X86::VR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp763 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
765 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
766 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1019 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getStoreOpcodeForSpill()
1105 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getLoadOpcodeForSpill()
1198 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
1199 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
1202 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
1250 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in LoadRegFromStackSlot()
1251 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in LoadRegFromStackSlot()
[all …]
H A DPPCVSXCopy.cpp59 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
H A DPPCVSXSwapRemoval.cpp167 return RC->hasSubClassEq(MRI->getRegClass(Reg)); in isRegInClass()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp120 if (RISCV::GPRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
123 else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
125 else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
147 if (RISCV::GPRRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
150 else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
152 else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp512 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
526 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
527 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
2657 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2661 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2705 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2723 if (AArch64::QQQRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2788 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
2792 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
2836 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp422 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
425 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
460 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
463 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp149 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
159 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
191 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
200 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
H A DARMBaseInstrInfo.cpp988 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
999 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1017 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1045 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1088 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1205 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1215 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1231 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1263 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1302 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
H A DThumbRegisterInfo.cpp49 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h111 return RC != this && hasSubClassEq(RC); in hasSubClass()
115 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
128 return RC->hasSubClassEq(this); in hasSuperClassEq()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp47 if (!RC.hasSubClassEq(&SubRC)) in verify()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp299 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
326 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp35 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
39 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
H A DSystemZInstrInfo.cpp580 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) || in canInsertSelect()
581 SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in canInsertSelect()
582 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in canInsertSelect()
607 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) { in insertSelect()
620 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) in insertSelect()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp891 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
899 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
903 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
907 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
911 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
923 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
956 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
965 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
968 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
971 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
H A DHexagonConstPropagation.cpp2351 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
2353 if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
2355 if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
H A DHexagonFrameLowering.cpp2045 if (HaveRC->hasSubClassEq(NewRC)) in optimizeSpillSlots()
2047 if (NewRC->hasSubClassEq(HaveRC)) in optimizeSpillSlots()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp60 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
80 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMachineFunction.cpp575 RC->hasSubClassEq(VRegRC))) && in addLiveIn()
H A DTargetInstrInfo.cpp450 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) in canFoldCopy()

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