Lines Matching refs:hasSubClassEq
988 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
999 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1006 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1017 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1024 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1045 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1065 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1088 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1113 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1205 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1215 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1221 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1231 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1237 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1263 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1280 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1302 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1325 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()