435   bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));  in canFoldIntoCSel()
512   if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||  in canInsertSelect()
513       AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in canInsertSelect()
526   if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||  in canInsertSelect()
527       AArch64::FPR32RegClass.hasSubClassEq(RC)) {  in canInsertSelect()
1076     } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&  in UpdateOperandRegClass()
2657     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2661     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2665     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2671     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2675     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2681     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2683     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2691     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2693     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2697     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2705     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2712     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2716     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2723     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2730     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2788     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2792     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2796     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2802     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2806     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2812     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2814     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2822     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2824     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2828     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2836     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2843     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2847     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2854     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2861     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()