Lines Matching refs:hasSubClassEq

891   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
895   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
899   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
903   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
907   } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
911   } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
923   } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
956   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
959   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
962   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
965   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
968   } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
971   } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
982   } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()