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Searched refs:getRegClass (Results 1 – 25 of 170) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h48 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
49 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
50 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
51 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
52 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
53 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
54 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
55 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
56 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp154 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
169 MRI.getRegClass(SrcReg) : in getCopyRegClasses()
177 MRI.getRegClass(DstReg) : in getCopyRegClasses()
218 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
242 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
286 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
312 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) in phiHasVGPROperands()
626 if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) in runOnMachineFunction()
697 DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
698 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
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H A DSIFixupVectorISel.cpp129 IdxRC = MRI.getRegClass(MI->getOperand(1).getReg()); in findSRegBaseAndIndex()
139 BaseRC = MRI.getRegClass(BaseReg); in findSRegBaseAndIndex()
145 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg))) in findSRegBaseAndIndex()
H A DSIInstrInfo.cpp1823 assert(MRI.getRegClass(FalseReg) == RC); in canInsertSelect()
1837 assert(MRI.getRegClass(FalseReg) == RC); in canInsertSelect()
3269 return MRI.getRegClass(Reg); in getOpRegClass()
3274 return RI.getRegClass(RCID); in getOpRegClass()
3384 MRI.getRegClass(Reg) : in isLegalRegOperand()
3599 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) in legalizeOperandsVOP3()
3914 MRI.getRegClass(MI.getOperand(i).getReg()); in legalizeOperands()
4637 MRI.getRegClass(Src0.getReg()) : in splitScalar64BitUnaryOp()
4761 MRI.getRegClass(Src0.getReg()) : in splitScalar64BitBinaryOp()
4766 MRI.getRegClass(Src1.getReg()) : in splitScalar64BitBinaryOp()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
H A DInstructionSelect.cpp171 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction()
172 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp150 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
152 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
154 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
156 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
158 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
160 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
162 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
H A DA15SDOptimizer.cpp140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
273 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
274 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
519 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
520 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
536 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
542 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
643 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp67 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in MaybeRewriteToDrop()
100 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); in MaybeRewriteToFallthrough()
150 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
H A DWebAssemblyExplicitLocals.cpp243 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
276 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
348 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
379 typeForRegClass(MRI.getRegClass(Reg))); in runOnMachineFunction()
H A DWebAssemblyRegColoring.cpp141 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
146 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC) in runOnMachineFunction()
H A DWebAssemblyMemIntrinsicResults.cpp172 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg)) in optimizeCall()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp132 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
201 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getRegClass() function in X86InstructionSelector
204 return getRegClass(Ty, RegBank); in getRegClass()
252 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
282 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
720 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
721 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
819 getRegClass(LLT::scalar(32), DstReg, MRI)); in selectZext()
895 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
896 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectAnyext()
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/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
133 MRI.getRegClass(AddendSrcReg)) in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
238 MRI.getRegClass(OldFMAReg))) in processBlock()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
162 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
223 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
251 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
335 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
469 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
535 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
592 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
633 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
650 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/InstPrinter/
H A DAMDGPUInstPrinter.cpp322 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(RegNo)) { in printRegOperand()
325 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(RegNo)) { in printRegOperand()
328 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(RegNo)) { in printRegOperand()
331 } else if (MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(RegNo)) { in printRegOperand()
334 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(RegNo)) { in printRegOperand()
340 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(RegNo)) { in printRegOperand()
343 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(RegNo)) { in printRegOperand()
346 } else if (MRI.getRegClass(AMDGPU::SGPR_256RegClassID).contains(RegNo)) { in printRegOperand()
349 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(RegNo)) { in printRegOperand()
352 } else if (MRI.getRegClass(AMDGPU::SGPR_512RegClassID).contains(RegNo)) { in printRegOperand()
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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp137 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
334 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
433 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
477 if (MRI->getRegClass(DR.R) != PredRC) in eliminatePredCopies()
479 if (MRI->getRegClass(SR.R) != PredRC) in eliminatePredCopies()
H A DHexagonSplitDouble.cpp229 if (MRI->getRegClass(R) == DoubleRC) in partitionRegisters()
267 if (MRI->getRegClass(T) != DoubleRC) in partitionRegisters()
504 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass); in collectIndRegsForLoop()
518 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC) in collectIndRegsForLoop()
520 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC) in collectIndRegsForLoop()
540 if (MRI->getRegClass(R) == DoubleRC) in collectIndRegsForLoop()
611 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) { in createHalfInstr()
677 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg()); in splitMemRef()
1007 if (MRI->getRegClass(DstR) == DoubleRC) { in splitInstr()
1111 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg()) in collapseRegPairs()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DRegAllocBase.cpp107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
134 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
H A DDetectDeadLanes.cpp159 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy()
255 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
374 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes()
439 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
488 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput()
H A DPeepholeOptimizer.cpp474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
571 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
669 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource()
731 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); in findNextSource()
761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
1232 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1426 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg)) in foldRedundantCopy()
1956 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) || in getNextSourceFromInsertSubreg()
H A DTargetRegisterInfo.cpp159 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
181 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass()
249 TRI->getRegClass(I + countTrailingZeros(Common)); in firstCommonClass()
483 RC = MRI.getRegClass(Reg); in getRegSizeInBits()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp110 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
117 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
119 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp38 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg()
39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp1255 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || in printVectorList()
1256 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || in printVectorList()
1257 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) in printVectorList()
1259 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || in printVectorList()
1260 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || in printVectorList()
1261 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) in printVectorList()
1263 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || in printVectorList()
1265 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg)) in printVectorList()
1278 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { in printVectorList()
1280 MRI.getRegClass(AArch64::FPR128RegClassID); in printVectorList()
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