Searched refs:getRegBitWidth (Results 1 – 12 of 12) sorted by relevance
95 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask()274 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch"); in evaluate()314 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate()372 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()701 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()756 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()768 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()830 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()862 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()967 uint16_t RW = getRegBitWidth(PD); in evaluate()[all …]
330 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth() function in BT::MachineEvaluator350 uint16_t BW = getRegBitWidth(RR); in getCell()709 uint16_t W = getRegBitWidth(Reg); in mask()734 uint16_t W = getRegBitWidth(RD); in evaluate()748 uint16_t WD = getRegBitWidth(RD); in evaluate()749 uint16_t WS = getRegBitWidth(RS); in evaluate()806 uint16_t DefBW = ME.getRegBitWidth(DefRR); in visitPHI()884 uint16_t DefBW = ME.getRegBitWidth(RD); in visitNonBranch()
1844 unsigned getRegBitWidth(unsigned Reg) const;1981 unsigned W = getRegBitWidth(DefR.Reg); in evaluate()2142 unsigned BW = getRegBitWidth(R1.Reg); in evaluate()2349 unsigned HexagonConstEvaluator::getRegBitWidth(unsigned Reg) const { in getRegBitWidth() function in HexagonConstEvaluator2687 unsigned W = getRegBitWidth(DefR.Reg); in evaluateHexCondMove()2739 unsigned BW = getRegBitWidth(DefR.Reg); in evaluateHexExt()2885 unsigned W = getRegBitWidth(R); in rewriteHexConstDefs()
397 uint16_t getRegBitWidth(const RegisterRef &RR) const;
130 if (AMDGPU::getRegBitWidth(IdxRC->getID()) != 64) in findSRegBaseAndIndex()140 if (AMDGPU::getRegBitWidth(BaseRC->getID()) != 64) in findSRegBaseAndIndex()
531 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 && in createsVALUHazard()543 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256); in createsVALUHazard()549 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64) in createsVALUHazard()
544 unsigned NumSubRegs = AMDGPU::getRegBitWidth(RC->getID()) / (EltSize * CHAR_BIT); in buildSpillLoadStore()1423 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()1459 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()1487 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()
529 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()536 if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64) in foldOperand()
1825 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32; in canInsertSelect()1839 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32; in canInsertSelect()
427 unsigned getRegBitWidth(unsigned RCID);430 unsigned getRegBitWidth(const MCRegisterClass &RC);
801 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() function832 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth() function833 return getRegBitWidth(RC.getID()); in getRegBitWidth()840 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
562 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printOperand()