| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 122 unsigned getOrder() const { return Order; } in getOrder() function
161 unsigned getOrder() const { return Order; } in getOrder() function
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| H A D | ScheduleDAGSDNodes.cpp | 727 unsigned DVOrder = DV->getOrder(); in ProcessSDDbgValues()
879 return LHS->getOrder() < RHS->getOrder(); in EmitSchedule()
893 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
919 assert((*DI)->getOrder() >= LastOrder && in EmitSchedule()
941 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; in EmitSchedule()
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| H A D | SelectionDAG.cpp | 7947 Dbg->getDebugLoc(), Dbg->getOrder()); in transferDbgValues()
7988 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder()); in salvageDebugInfo()
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| /freebsd-12.1/stand/ficl/ |
| H A D | search.c | 110 static void getOrder(FICL_VM *pVM) in getOrder() function
371 dictAppendWord(dp, "get-order", getOrder, FW_DEFAULT); in ficlCompileSearch()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
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| H A D | AllocationOrder.h | 50 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder() function
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| H A D | RegAllocBase.cpp | 134 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
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| H A D | BreakFalseDeps.cpp | 145 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| H A D | RegAllocGreedy.cpp | 1020 for (auto PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight()
1105 unsigned OrderLimit = Order.getOrder().size(); in tryEvict()
1124 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) { in tryEvict()
1536 for (auto PhysReg : Order.getOrder()) { in splitCanCauseLocalSpill()
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| H A D | CriticalAntiDepBreaker.cpp | 398 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | AggressiveAntiDepBreaker.cpp | 633 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| H A D | RegAllocFast.cpp | 586 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 97 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() function
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1039 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
1080 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " in runMCDesc()
1223 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1373 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1386 if (RC.getOrder(oi).empty()) in runTargetDesc()
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| H A D | CodeGenRegisters.h | 422 ArrayRef<Record*> getOrder(unsigned No = 0) const {
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| H A D | AsmMatcherEmitter.cpp | 1223 RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); in buildRegisterClasses()
1299 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), in buildRegisterClasses()
1300 RC.getOrder().end())]; in buildRegisterClasses()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 520 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/ |
| H A D | CGOpenMPRuntime.h | 450 unsigned getOrder() const { return Order; } in getOrder() function
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| H A D | CGOpenMPRuntime.cpp | 3988 GetMDInt(Line), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
3991 OrderedEntries[E.getOrder()] = &E; in createOffloadEntriesAndInfoMetadata()
3992 ParentFunctions[E.getOrder()] = ParentName; in createOffloadEntriesAndInfoMetadata()
4016 GetMDInt(E.getFlags()), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
4019 OrderedEntries[E.getOrder()] = &E; in createOffloadEntriesAndInfoMetadata()
4035 StringRef FnName = ParentFunctions[CE->getOrder()]; in createOffloadEntriesAndInfoMetadata()
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| H A D | CGAtomic.cpp | 778 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr()
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| /freebsd-12.1/contrib/llvm/tools/clang/lib/AST/ |
| H A D | StmtPrinter.cpp | 1596 PrintExpr(Node->getOrder()); in VisitAtomicExpr()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 586 for (unsigned Reg : RegClassInfo.getOrder(&RegClass)) in findFreeReg()
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| /freebsd-12.1/contrib/llvm/tools/clang/include/clang/AST/ |
| H A D | Expr.h | 5473 Expr *getOrder() const { in getOrder() function
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