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Searched refs:getLocReg (Results 1 – 25 of 29) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DCallingConvLower.cpp74 for (MCRegAliasIterator AI(ValAssign.getLocReg(), &TRI, true); in IsShadowAllocatedReg()
239 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
296 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp117 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
163 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
164 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
353 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
396 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
397 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
H A DARMFastISel.cpp2004 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2020 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2021 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2067 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2068 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2070 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2071 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2088 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
2089 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2166 unsigned DstReg = VA.getLocReg(); in SelectRet()
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H A DARMISelLowering.cpp1921 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2533 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2539 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2554 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2558 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2560 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2564 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
2569 RetOps.push_back(DAG.getRegister(VA.getLocReg(), in LowerReturn()
3497 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in GetF64FormalArgument()
3511 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in GetF64FormalArgument()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp243 MRI.addLiveIn(VA.getLocReg(), VRegs[OrigArgIdx]); in lowerFormalArguments()
244 MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); in lowerFormalArguments()
245 MIRBuilder.buildCopy(VRegs[OrigArgIdx], VA.getLocReg()); in lowerFormalArguments()
H A DSIISelLowering.cpp2002 unsigned Reg = VA.getLocReg(); in LowerFormalArguments()
2173 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn()
2175 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2225 Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
2595 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp255 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
345 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
421 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
434 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
449 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
600 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
908 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
1065 unsigned Offset = argSize * (VA.getLocReg() - firstReg); in fixupVariableFloatArgs()
1169 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1201 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerCall_64()
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/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp241 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
349 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
437 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
442 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
475 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp998 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
1071 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); in unpackF64OnRV32DSoftABI()
1074 if (VA.getLocReg() == RISCV::X17) { in unpackF64OnRV32DSoftABI()
1083 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); in unpackF64OnRV32DSoftABI()
1394 unsigned RegLo = VA.getLocReg(); in LowerCall()
1450 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
1539 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
1545 assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment"); in LowerCall()
1609 unsigned RegLo = VA.getLocReg(); in LowerReturn()
1620 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp287 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
382 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue); in lowerCallResult()
495 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCallArguments()
665 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
670 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp132 unsigned PhysReg = VA.getLocReg(); in assignValueToReg()
216 unsigned PhysReg = VA.getLocReg(); in assignValueToReg()
327 VA.getLocReg(), VA.getLocVT(), LocInfo); in setLocInfo()
H A DMipsFastISel.cpp1229 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1230 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1300 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1301 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1726 unsigned DestReg = VA.getLocReg(); in selectRet()
1767 RetRegs.push_back(VA.getLocReg()); in selectRet()
H A DMipsISelLowering.cpp3088 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
3130 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3277 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3444 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
3631 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
3635 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp141 Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA); in handleAssignments()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp464 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
557 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
561 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
686 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
787 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp637 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
747 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
753 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
832 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
932 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1081 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1232 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1335 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), in LowerCallResult()
1406 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1410 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FastISel.cpp1229 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1258 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
1267 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
3416 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
3417 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3566 unsigned SrcReg = VA.getLocReg(); in fastLowerCall()
3585 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
H A DX86ISelLowering.cpp2485 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && in LowerReturn()
2500 if (VA.getLocReg() == X86::FP0 || in LowerReturn()
2501 VA.getLocReg() == X86::FP1) { in LowerReturn()
2515 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
2716 Reg = MF.addLiveIn(VA.getLocReg(), RC); in getv64i1Argument()
2718 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in getv64i1Argument()
2818 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in LowerCallResult()
3254 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
3812 switch (VA.getLocReg()) { in LowerCall()
4389 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in IsEligibleForTailCallOptimization()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1063 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1157 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1307 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1495 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1500 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp218 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
222 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
287 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
301 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
435 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
759 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1518 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1728 unsigned RetReg = VA.getLocReg(); in SelectRet()
1752 RetRegs.push_back(VA.getLocReg()); in SelectRet()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3083 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
3084 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3148 .addReg(RVLocs[0].getLocReg()); in finishCall()
3149 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
3841 unsigned DestReg = VA.getLocReg(); in selectRet()
3879 RetRegs.push_back(VA.getLocReg()); in selectRet()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1154 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1248 unsigned Reg = VA.getLocReg(); in canUseSiblingCall()
1331 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
1423 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), in LowerCall()
1492 unsigned Reg = VA.getLocReg(); in LowerReturn()

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