2419   RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));  in Passv64i1ArgInRegs()
2420   RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));  in Passv64i1ArgInRegs()
2460       MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());  in LowerReturn()
2485          VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&  in LowerReturn()
2500     if (VA.getLocReg() == X86::FP0 ||  in LowerReturn()
2501         VA.getLocReg() == X86::FP1) {  in LowerReturn()
2515         if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {  in LowerReturn()
2541         MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());  in LowerReturn()
2543       RegsToPass.push_back(std::make_pair(VA.getLocReg(), ValToCopy));  in LowerReturn()
2716     Reg = MF.addLiveIn(VA.getLocReg(), RC);  in getv64i1Argument()
2718     Reg = MF.addLiveIn(NextVA.getLocReg(), RC);  in getv64i1Argument()
2724       DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);  in getv64i1Argument()
2727       DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);  in getv64i1Argument()
2803       for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);  in LowerCallResult()
2818     if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&  in LowerCallResult()
2833       Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)  in LowerCallResult()
3254         unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);  in LowerFormalArguments()
3807       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));  in LowerCall()
3812         switch (VA.getLocReg()) {  in LowerCall()
4389       if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)  in IsEligibleForTailCallOptimization()
4462         unsigned Reg = VA.getLocReg();  in IsEligibleForTailCallOptimization()