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Searched refs:SINT_TO_FP (Results 1 – 25 of 30) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp193 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
279 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
281 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
283 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
285 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
287 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
289 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
291 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
293 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
295 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp165 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
170 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
763 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
4882 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
4884 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
4902 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
7449 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
7450 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
7481 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
8016 case ISD::SINT_TO_FP: in LowerOperation()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp318 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
319 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
320 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
326 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
327 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
328 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
334 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
335 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
341 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
350 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp240 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
241 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
242 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
557 setTargetDAGCombine(ISD::SINT_TO_FP); in AArch64TargetLowering()
651 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
670 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
672 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom); in AArch64TargetLowering()
2449 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
2939 case ISD::SINT_TO_FP: in LowerOperation()
9213 bool IsSigned = Opc == ISD::SINT_TO_FP; in performFDivCombine()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1427 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
1428 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost()
1429 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, in getCastInstrCost()
1430 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
1431 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, in getCastInstrCost()
1432 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, in getCastInstrCost()
1433 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, in getCastInstrCost()
1434 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, in getCastInstrCost()
1435 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, in getCastInstrCost()
1519 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, in getCastInstrCost()
[all …]
H A DX86IntrinsicsInfo.h509 ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND), //er
563 ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
567 ISD::SINT_TO_FP, 0),
569 ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
H A DX86ISelLowering.cpp247 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Expand); in X86TargetLowering()
736 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
1496 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal); in X86TargetLowering()
1587 setOperationAction(ISD::SINT_TO_FP, VT, Legal); in X86TargetLowering()
1884 setTargetDAGCombine(ISD::SINT_TO_FP); in X86TargetLowering()
17299 assert((Op.getOpcode() == ISD::SINT_TO_FP || in LowerI64IntToFP_AVX512DQ()
26760 case ISD::SINT_TO_FP: { in ReplaceNodeResults()
40121 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineUIntToFP()
40153 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineSIntToFP()
40169 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, Trunc); in combineSIntToFP()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp438 case ISD::SINT_TO_FP: in LegalizeOp()
486 case ISD::SINT_TO_FP: in Promote()
1112 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || in ExpandUINT_TO_FLOAT()
1138 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); in ExpandUINT_TO_FLOAT()
1140 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); in ExpandUINT_TO_FLOAT()
H A DLegalizeFloatTypes.cpp109 case ISD::SINT_TO_FP: in SoftenFloatResult()
708 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in SoftenFloatRes_XINT_TO_FP()
1098 case ISD::SINT_TO_FP: in ExpandFloatResult()
1465 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; in ExpandFloatRes_XINT_TO_FP()
1477 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); in ExpandFloatRes_XINT_TO_FP()
1932 case ISD::SINT_TO_FP: in PromoteFloatResult()
H A DLegalizeDAG.cpp994 case ISD::SINT_TO_FP: in LegalizeOp()
2388 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2456 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP()
2457 OpToUse = ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
2865 case ISD::SINT_TO_FP: in ExpandNode()
2866 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, in ExpandNode()
4105 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
4165 case ISD::SINT_TO_FP: in PromoteNode()
4167 Node->getOpcode() == ISD::SINT_TO_FP, dl); in PromoteNode()
H A DSelectionDAGDumper.cpp316 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
H A DLegalizeVectorTypes.cpp100 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
542 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
785 case ISD::SINT_TO_FP: in SplitVectorResult()
1725 case ISD::SINT_TO_FP: in SplitVectorOperand()
2501 case ISD::SINT_TO_FP: in WidenVectorResult()
3710 case ISD::SINT_TO_FP: in WidenVectorOperand()
H A DFastISel.cpp435 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1886 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
H A DLegalizeIntegerTypes.cpp1063 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; in PromoteIntegerOperand()
3181 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; in ExpandIntegerOperand()
3558 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ in ExpandIntOp_UINT_TO_FP()
3560 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
H A DTargetLowering.cpp4454 !isOperationLegalOrCustom(ISD::SINT_TO_FP, SrcVT) || in expandUINT_TO_FP()
4461 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Src); in expandUINT_TO_FP()
4469 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Or); in expandUINT_TO_FP()
H A DDAGCombiner.cpp1561 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); in visit()
11898 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && in foldFPToIntToFP()
11919 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); in visitSINT_TO_FP()
11923 if (!hasOperation(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
11981 hasOperation(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
11984 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); in visitUINT_TO_FP()
12013 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
12018 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; in FoldIntToFPToInt()
H A DSelectionDAG.cpp3869 case ISD::SINT_TO_FP: in isKnownNeverNaN()
4108 case ISD::SINT_TO_FP: { in getNode()
4112 Opcode==ISD::SINT_TO_FP, in getNode()
4247 case ISD::SINT_TO_FP: in getNode()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h478 SINT_TO_FP, enumerator
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp196 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
202 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
369 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
1063 setTargetDAGCombine(ISD::SINT_TO_FP); in PPCTargetLowering()
7246 if (UI->getOpcode() != ISD::SINT_TO_FP && in directMoveIsProfitable()
7269 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP; in LowerINT_TO_FPDirectMove()
7315 bool SignedConv = Opc == ISD::SINT_TO_FP; in LowerINT_TO_FPVector()
12316 if (FirstInput.getOpcode() != ISD::SINT_TO_FP && in DAGCombineBuildVector()
12359 assert((N->getOpcode() == ISD::SINT_TO_FP || in combineFPToIntToFP()
12383 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in combineFPToIntToFP()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1510 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1512 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3019 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3367 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3374 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp381 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
416 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
1163 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1489 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2443 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
H A DSIISelLowering.cpp465 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in SITargetLowering()
483 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote); in SITargetLowering()
677 setTargetDAGCombine(ISD::SINT_TO_FP); in SITargetLowering()
7610 case ISD::SINT_TO_FP: in fp16SrcZerosHighBits()
7704 N0.getOpcode() == ISD::SINT_TO_FP)) { in performRcpCombine()
8971 case ISD::SINT_TO_FP: in PerformDAGCombine()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1531 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1532 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1533 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1489 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp352 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); in addMSAIntType()
1836 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()

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