Home
last modified time | relevance | path

Searched refs:Reg0 (Results 1 – 20 of 20) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h119 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
123 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
125 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
133 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
135 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsSEFrameLowering.cpp464 unsigned Reg0 = in emitPrologue() local
470 std::swap(Reg0, Reg1); in emitPrologue()
473 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
482 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
486 std::swap(Reg0, Reg1); in emitPrologue()
489 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp146 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
150 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
159 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
165 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
167 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
172 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
190 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
200 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
206 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
209 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII() argument
[all …]
H A DMipsMCCodeEmitter.cpp99 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
104 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
105 if (Reg0 < Reg1) in LowerCompactBranch()
108 if (Reg0 >= Reg1) in LowerCompactBranch()
112 if (Reg1 >= Reg0) in LowerCompactBranch()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp241 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
242 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
246 if (TargetRegisterInfo::isVirtualRegister(Reg0)) { in runOnMachineFunction()
248 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
H A DHexagonBitTracker.cpp317 unsigned Reg0 = Reg[0].Reg; in evaluate() local
843 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
845 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
847 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
849 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCRegisterInfo.h636 uint16_t Reg0 = 0; variable
644 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
650 return Reg0;
655 return Reg0; in isValid()
661 Reg0 = Reg1;
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1822 Ops.push_back(Reg0); in SelectVLD()
1852 Ops.push_back(Reg0); in SelectVLD()
2005 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
2024 Ops.push_back(Reg0); in SelectVST()
2130 Ops.push_back(Reg0); in SelectVLDSTLane()
2326 getAL(CurDAG, dl), Reg0, Reg0 }; in tryV6T2BitfieldExtractOp()
2337 getAL(CurDAG, dl), Reg0, Reg0 }; in tryV6T2BitfieldExtractOp()
2692 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select()
2696 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select()
2711 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select()
[all …]
H A DThumb2SizeReduction.cpp747 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
753 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
756 if (Reg0 != Reg2) { in ReduceTo2Addr()
759 if (Reg1 != Reg0) in ReduceTo2Addr()
766 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
771 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
778 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
H A DARMAsmPrinter.cpp322 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
323 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp225 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
248 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
263 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp470 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
473 .addImm(Reg0) in InsertSEH()
483 unsigned Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
485 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
491 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
521 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
524 .addImm(Reg0) in InsertSEH()
532 unsigned Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
534 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
540 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp165 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0; in commuteInstructionImpl() local
187 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
190 Reg0 = Reg2; in commuteInstructionImpl()
192 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
195 Reg0 = Reg1; in commuteInstructionImpl()
209 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
H A DRegisterCoalescer.cpp2429 unsigned Reg0; in valuesIdentical() local
2430 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2431 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2441 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2447 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp1375 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1378 printRegName(O, Reg0); in printVectorListTwo()
1388 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1391 printRegName(O, Reg0); in printVectorListTwoSpaced()
1443 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1446 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1490 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1493 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp218 unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, in buildEXP() argument
225 .addReg(Reg0) in buildEXP()
262 unsigned Reg0 = I.getOperand(3).getReg(); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
269 MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM, in selectG_INTRINSIC_W_SIDE_EFFECTS()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h407 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
H A DAMDGPUBaseInfo.cpp693 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { in isRegIntersect() argument
694 for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) { in isRegIntersect()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp384 unsigned Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
394 if (Reg0 == Reg1) { in commuteInstructionImpl()
414 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
417 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp4940 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0; in foldMemoryOperandImpl() local
4950 if ((HasDef && Reg0 == Reg1 && Tied1) || in foldMemoryOperandImpl()
4951 (HasDef && Reg0 == Reg2 && Tied2)) in foldMemoryOperandImpl()