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Searched refs:INSERT_VECTOR_ELT (Results 1 – 25 of 28) sorted by relevance

12

/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp388 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
396 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
H A DPPCISelLowering.cpp616 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
821 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in PPCTargetLowering()
822 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in PPCTargetLowering()
873 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in PPCTargetLowering()
874 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in PPCTargetLowering()
898 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand); in PPCTargetLowering()
947 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand); in PPCTargetLowering()
988 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand); in PPCTargetLowering()
9201 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && in LowerINSERT_VECTOR_ELT()
9661 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h332 INSERT_VECTOR_ELT, enumerator
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp210 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
211 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
212 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
213 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
279 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering()
479 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
735 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1890 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
H A DSIISelLowering.cpp260 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
289 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom); in SITargetLowering()
318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom); in SITargetLowering()
319 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom); in SITargetLowering()
506 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
683 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in SITargetLowering()
3648 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
3813 case ISD::INSERT_VECTOR_ELT: { in ReplaceNodeResults()
7823 case ISD::INSERT_VECTOR_ELT: { in isCanonicalized()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp439 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
443 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
733 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
1220 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
1224 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
2393 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
2619 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx], in CollectOpsToWiden()
3257 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
4155 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
H A DSelectionDAGDumper.cpp272 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
H A DLegalizeIntegerTypes.cpp98 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult()
1054 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand()
3176 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand()
3808 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
H A DLegalizeDAG.cpp2906 case ISD::INSERT_VECTOR_ELT: in ExpandNode()
4108 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { in PromoteNode()
4457 case ISD::INSERT_VECTOR_ELT: { in PromoteNode()
4500 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT, in PromoteNode()
H A DSelectionDAG.cpp3048 case ISD::INSERT_VECTOR_ELT: { in computeKnownBits()
3620 case ISD::INSERT_VECTOR_ELT: { in ComputeNumSignBits()
5007 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { in getNode()
5312 case ISD::INSERT_VECTOR_ELT: { in getNode()
H A DDAGCombiner.cpp1581 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); in visit()
15538 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
15543 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, in visitINSERT_VECTOR_ELT()
15546 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), in visitINSERT_VECTOR_ELT()
15714 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
17541 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceShuffleOfInsert()
17560 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Shuf), Op0.getValueType(), in replaceShuffleOfInsert()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp233 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); in WebAssemblyTargetLowering()
238 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); in WebAssemblyTargetLowering()
898 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp99 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
190 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
1556 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1431 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1475 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
2763 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp324 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType()
377 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
1923 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2486 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp162 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
716 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in ARMTargetLowering()
3691 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3694 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
6489 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops); in LowerBUILD_VECTOR()
6571 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
7143 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
7147 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
8045 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
11502 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp328 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
415 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
416 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
4528 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
4643 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, in lowerSCALAR_TO_VECTOR()
4673 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, in lowerINSERT_VECTOR_ELT()
4878 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
H A DSystemZISelDAGToDAG.cpp1517 case ISD::INSERT_VECTOR_ELT: { in Select()
H A DSystemZOperators.td286 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp582 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in AArch64TargetLowering()
779 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
2908 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
6705 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()
7421 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
7477 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
7490 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in LowerINSERT_VECTOR_ELT()
7515 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, in LowerINSERT_VECTOR_ELT()
10238 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
11236 case ISD::INSERT_VECTOR_ELT: in PerformDAGCombine()
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td409 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
542 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp711 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in X86TargetLowering()
907 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1280 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1356 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1525 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1628 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
7689 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT)) in buildFromShuffleMostly()
7855 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
8914 (isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT) || in LowerBUILD_VECTOR()
37380 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, in reduceMaskedLoadToScalarLoad()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1505 case InsertElement: return ISD::INSERT_VECTOR_ELT; in InstructionOpcodeToISD()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp995 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo, in LowerCall_32()
1001 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi, in LowerCall_32()

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