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Searched refs:GPR32RegClass (Results 1 – 25 of 27) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp330 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
360 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
416 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
438 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
766 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
770 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
774 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
963 ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectBranch()
1036 RC = &Mips::GPR32RegClass; in selectSelect()
1128 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in selectFPToInt()
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H A DMipsMachineFunction.cpp45 return Mips::GPR32RegClass; in getGlobalBaseRegClass()
61 : Mips::GPR32RegClass; in createEhDataRegsFI()
73 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI()
H A DMipsOptionRecord.h48 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
67 const MCRegisterClass *GPR32RegClass; variable
H A DMipsInstructionSelector.cpp84 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in selectCopy()
186 unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
211 unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
248 unsigned Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
H A DMipsSEFrameLowering.cpp318 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64()
386 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64()
423 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
592 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptPrologueStub()
721 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
755 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptEpilogueStub()
894 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
911 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
H A DMipsSERegisterInfo.cpp57 return &Mips::GPR32RegClass; in intRegClass()
226 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
H A DMipsSEInstrInfo.cpp91 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
92 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
119 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
260 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
338 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
620 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
H A DMipsSubtarget.cpp219 : &Mips::GPR32RegClass); in getCriticalPathRCs()
H A DMips16InstrInfo.cpp77 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
79 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
H A DMipsSEISelLowering.cpp68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
2998 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitBPOSGE32()
3067 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitMSACBranchPseudo()
3299 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3484 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass in emitST_F16_PSEUDO()
3486 const bool UsingMips32 = RC == &Mips::GPR32RegClass; in emitST_F16_PSEUDO()
3487 unsigned Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitST_F16_PSEUDO()
3539 const bool UsingMips32 = RC == &Mips::GPR32RegClass; in emitLD_F16_PSEUDO()
3548 unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitLD_F16_PSEUDO()
3629 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPROUND_PSEUDO()
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H A DMipsRegisterInfo.cpp55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
H A DMipsAsmPrinter.cpp333 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
352 } else if (Mips::GPR32RegClass.contains(Reg)) in printSavedRegsBitmask()
H A DMipsSEISelDAGToDAG.cpp152 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp273 assert(ARC::GPR32RegClass.contains(SrcReg) && in copyPhysReg()
275 assert(ARC::GPR32RegClass.contains(DestReg) && in copyPhysReg()
299 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
326 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
H A DARCRegisterInfo.cpp61 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in ReplaceFrameIndex()
67 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
207 assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand"); in eliminateFrameIndex()
H A DARCExpandPseudos.cpp63 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore()
H A DARCISelLowering.cpp77 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
494 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
539 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
H A DARCFrameLowering.cpp420 const TargetRegisterClass *RC = &ARC::GPR32RegClass; in processFunctionBeforeFrameFinalized()
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp39 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
139 else if (RC == &BPF::GPR32RegClass) in storeRegToStackSlot()
159 else if (RC == &BPF::GPR32RegClass) in loadRegFromStackSlot()
H A DBPFISelLowering.cpp65 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
240 &BPF::GPR32RegClass); in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp423 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
1730 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
1836 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
2549 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2568 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2692 RC = &AArch64::GPR32RegClass; in selectSelect()
2996 RC = &AArch64::GPR32RegClass; in fastLowerArguments()
3945 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectTrunc()
4812 case MVT::i32: RC = &AArch64::GPR32RegClass; break; in selectBitCast()
4911 RC = &AArch64::GPR32RegClass; in selectSDiv()
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H A DAArch64InstructionSelector.cpp158 : &AArch64::GPR32RegClass; in getRegClassForTypeOnBank()
886 DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass; in select()
945 AArch64::GPR32RegClass, MRI); in select()
980 AArch64::GPR32RegClass, MRI); in select()
1214 } else if (DstRC == &AArch64::GPR32RegClass && in select()
1299 if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) { in select()
1483 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
1493 unsigned Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
H A DAArch64InstrInfo.cpp629 RC = &AArch64::GPR32RegClass; in insertSelect()
1583 return (AArch64::GPR32RegClass.contains(DstReg) || in isGPRCopy()
2587 AArch64::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
2592 if (AArch64::GPR32RegClass.contains(DestReg) && in copyPhysReg()
3113 FillRC = &AArch64::GPR32RegClass; in foldMemoryOperandImpl()
4127 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
4142 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
4164 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
4207 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
4234 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
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H A DAArch64CollectLOH.cpp464 for (MCPhysReg Reg : AArch64::GPR32RegClass) in handleNormalInst()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp85 if (GPR32RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()

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