330   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLogicalOp()
346     unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in fastMaterializeAlloca()
360   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeInt()
397     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);  in materializeFP()
403     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);  in materializeFP()
405         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);  in materializeFP()
416   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeGV()
438   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeExternalCallSym()
654     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
660     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
672     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
678     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
690     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
696     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
742     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
743     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
766     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
770     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
774     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
963       ZExtCondReg = createResultReg(&Mips::GPR32RegClass);  in selectBranch()
989   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectCmp()
1036     RC = &Mips::GPR32RegClass;  in selectSelect()
1055   unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);  in selectSelect()
1128   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in selectFPToInt()
1387       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);  in fastLowerArguments()
1407       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);  in fastLowerArguments()
1598     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1609           TempReg[i] = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1622         unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1630           TempReg[i] = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1819   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectIntExt()
1840   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitIntSExt32r1()
1908   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in emitIntExt()
1944   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectDivRem()
1963   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()
1975     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()
2101     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in getRegEnsuringSimpleIntegerWidening()
2112         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);  in simplifyAddress()
2113     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in simplifyAddress()