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Searched refs:FP_ROUND (Results 1 – 24 of 24) sorted by relevance

/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h538 FP_ROUND, enumerator
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp95 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
763 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
865 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); in SoftenFloatOp_FP_ROUND()
1023 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), in SoftenFloatOp_STORE()
1562 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
1653 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
1927 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
2161 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL))); in PromoteFloatRes_XINT_TO_FP()
H A DLegalizeVectorTypes.cpp54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
274 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecRes_FP_ROUND()
561 case ISD::FP_ROUND: in ScalarizeVectorOperand()
688 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
777 case ISD::FP_ROUND: in SplitVectorResult()
1505 if (N->getOpcode() == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
1708 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
2315 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
2352 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); in SplitVecOp_FP_ROUND()
2353 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); in SplitVecOp_FP_ROUND()
[all …]
H A DLegalizeVectorOps.cpp408 case ISD::FP_ROUND: in LegalizeOp()
526 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); in Promote()
H A DLegalizeDAG.cpp2802 case ISD::FP_ROUND: in ExpandNode()
3109 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
4268 TruncOp = ISD::FP_ROUND; in PromoteNode()
4276 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
4336 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4344 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4360 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4382 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
H A DSelectionDAGDumper.cpp311 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
H A DDAGCombiner.cpp761 case ISD::FP_ROUND: in isNegatibleForFree()
832 case ISD::FP_ROUND: in GetNegatedExpression()
8464 CastOpcode == ISD::FP_ROUND) && in matchVSelectOpSizesWithSetCC()
8490 if (CastOpcode == ISD::FP_ROUND) { in matchVSelectOpSizesWithSetCC()
11656 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
11749 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
12087 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
12150 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
12164 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
12169 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, in visitFP_EXTEND()
[all …]
H A DSelectionDAG.cpp1097 : getNode(ISD::FP_ROUND, DL, VT, Op, getIntPtrConstant(0, DL)); in getFPExtendOrRound()
3864 case ISD::FP_ROUND: { in isKnownNeverNaN()
4277 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
4902 case ISD::FP_ROUND: in getNode()
5146 if (Opcode == ISD::FP_ROUND) { in getNode()
H A DSelectionDAGBuilder.cpp319 ISD::FP_ROUND, DL, ValueVT, Val, in getCopyFromParts()
3089 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, in visitFPTrunc()
5700 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16, in visitIntrinsicCall()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp144 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
149 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
H A DARMISelLowering.cpp662 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in ARMTargetLowering()
769 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in ARMTargetLowering()
8075 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG); in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1717 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1745 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1746 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3049 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h345 X86_INTRINSIC_DATA(avx_cvt_pd2_ps_256,CVTPD2PS, ISD::FP_ROUND, 0),
517 ISD::FP_ROUND, X86ISD::VFPROUND_RND),
H A DX86TargetTransformInfo.cpp1304 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
1396 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
1474 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, in getCastInstrCost()
H A DX86ISelDAGToDAG.cpp789 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) in PreprocessISelDAG()
821 if (N->getOpcode() == ISD::FP_ROUND) in PreprocessISelDAG()
H A DX86ISelLowering.cpp951 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom); in X86TargetLowering()
1131 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); in X86TargetLowering()
2840 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, in LowerCallResult()
17774 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, in LowerUINT_TO_FP()
18664 Sign = DAG.getNode(ISD::FP_ROUND, dl, VT, Sign, DAG.getIntPtrConstant(1, dl)); in LowerFCOPYSIGN()
21817 assert(IntrData->Opc0 == ISD::FP_ROUND && "Unexpected opcode!"); in LowerINTRINSIC_WO_CHAIN()
26792 case ISD::FP_ROUND: { in ReplaceNodeResults()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2469 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2496 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3710 case ISD::FP_ROUND: { in performFNegCombine()
3715 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3724 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
H A DR600ISelLowering.cpp275 setTargetDAGCombine(ISD::FP_ROUND); in R600TargetLowering()
1850 case ISD::FP_ROUND: { in PerformDAGCombine()
H A DSIISelLowering.cpp199 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
478 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in SITargetLowering()
3654 case ISD::FP_ROUND: in LowerOperation()
6702 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
7608 case ISD::FP_ROUND: in fp16SrcZerosHighBits()
7742 case ISD::FP_ROUND: in isCanonicalized()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp246 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
247 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
399 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
405 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
653 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
2410 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
2434 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
2896 case ISD::FP_ROUND: in LowerOperation()
4525 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
5192 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp857 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
858 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
908 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
7382 Value = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
7532 FP = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
7605 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
7867 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
12031 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl, in combineElementTruncationToVectorTruncation()
12071 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
12450 FP = DAG.getNode(ISD::FP_ROUND, dl, in combineFPToIntToFP()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1490 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td447 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp529 setTargetDAGCombine(ISD::FP_ROUND); in SystemZTargetLowering()
5506 if (OtherRound.getOpcode() == ISD::FP_ROUND && in combineFP_ROUND()
5833 case ISD::FP_ROUND: return combineFP_ROUND(N, DCI); in PerformDAGCombine()