| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 594 FMINNUM, FMAXNUM, enumerator
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| H A D | TargetLowering.h | 862 case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break; in getStrictFPOperationAction()
2161 case ISD::FMAXNUM: in isCommutativeBinOp()
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| H A D | BasicTTIImpl.h | 1190 ISDs.push_back(ISD::FMAXNUM);
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoops.cpp | 335 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR()
404 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
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| H A D | PPCISelLowering.cpp | 924 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal); in PPCTargetLowering()
969 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in PPCTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 389 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom); in SITargetLowering()
391 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom); in SITargetLowering()
574 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom); in SITargetLowering()
665 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering()
3665 case ISD::FMAXNUM: in LowerOperation()
5186 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
7631 case ISD::FMAXNUM: in fp16SrcZerosHighBits()
7778 case ISD::FMAXNUM: in isCanonicalized()
7991 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc()
8284 case ISD::FMAXNUM: in performExtractVectorEltCombine()
[all …]
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| H A D | AMDGPUISelLowering.cpp | 311 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
445 setOperationAction(ISD::FMAXNUM, VT, Expand); in AMDGPUTargetLowering()
552 case ISD::FMAXNUM: in fnegFoldsIntoOp()
3536 case ISD::FMAXNUM: in inverseMinMax()
3539 return ISD::FMAXNUM; in inverseMinMax()
3647 case ISD::FMAXNUM: in performFNegCombine()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 386 case ISD::FMAXNUM: in LegalizeOp()
779 case ISD::FMAXNUM: in Expand()
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| H A D | SelectionDAGDumper.cpp | 180 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 78 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
1072 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult()
1915 case ISD::FMAXNUM: in PromoteFloatResult()
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| H A D | LegalizeVectorTypes.cpp | 115 case ISD::FMAXNUM: in ScalarizeVectorResult()
807 case ISD::FMAXNUM: in SplitVectorResult()
1846 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; in SplitVecOp_VECREDUCE()
2421 case ISD::FMAXNUM: in WidenVectorResult()
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| H A D | SelectionDAGBuilder.cpp | 3013 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect()
3016 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) in visitSelect()
3017 Opc = ISD::FMAXNUM; in visitSelect()
3021 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? in visitSelect()
3022 ISD::FMAXNUM : ISD::FMAXIMUM; in visitSelect()
5618 : ISD::FMAXNUM; in visitIntrinsicCall()
7056 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
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| H A D | LegalizeDAG.cpp | 3065 case ISD::FMAXNUM: { in ExpandNode()
3829 case ISD::FMAXNUM: in ConvertNodeToLibcall()
4330 case ISD::FMAXNUM: in PromoteNode()
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| H A D | SelectionDAG.cpp | 3892 case ISD::FMAXNUM: { in isKnownNeverNaN()
7658 case ISD::STRICT_FMAXNUM: NewOpc = ISD::FMAXNUM; break; in mutateStrictFPToFP()
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| H A D | DAGCombiner.cpp | 1572 case ISD::FMAXNUM: return visitFMAXNUM(N); in visit()
7241 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; in combineMinNumMaxNum()
7256 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; in combineMinNumMaxNum()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 126 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in RISCVTargetLowering()
138 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in RISCVTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 454 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SystemZTargetLowering()
459 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
464 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in SystemZTargetLowering()
469 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
474 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); in SystemZTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 602 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1426 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
1520 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 525 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in ARMTargetLowering()
1126 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in ARMTargetLowering()
1128 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1130 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1140 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in ARMTargetLowering()
1158 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1160 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); in ARMTargetLowering()
3368 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
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| /freebsd-12.1/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 567 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) { in NVPTXTargetLowering()
574 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in NVPTXTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 389 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in AArch64TargetLowering()
454 setOperationAction(ISD::FMAXNUM, Ty, Legal); in AArch64TargetLowering()
467 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in AArch64TargetLowering()
822 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
9970 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 421 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp,
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 160 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 684 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand); in X86TargetLowering()
1873 setTargetDAGCombine(ISD::FMAXNUM); in X86TargetLowering()
38951 auto MinMaxOp = N->getOpcode() == ISD::FMAXNUM ? X86ISD::FMAX : X86ISD::FMIN; in combineFMinNumFMaxNum()
41551 case ISD::FMAXNUM: return combineFMinNumFMaxNum(N, DAG, Subtarget); in PerformDAGCombine()
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