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Searched refs:DefReg (Results 1 – 25 of 25) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp254 unsigned DefReg = Def.getReg(); in transferUsedLanes() local
255 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
289 unsigned DefReg = Def.getReg(); in transferDefinedLanesStep() local
290 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in transferDefinedLanesStep()
292 unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg); in transferDefinedLanesStep()
432 unsigned DefReg = Def.getReg(); in determineInitialUsedLanes() local
435 if (TargetRegisterInfo::isVirtualRegister(DefReg)) { in determineInitialUsedLanes()
474 unsigned DefReg = Def.getReg(); in isUndefInput() local
475 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in isUndefInput()
477 unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg); in isUndefInput()
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H A DTailDuplicator.cpp344 unsigned DefReg = MI->getOperand(0).getReg(); in processPHI() local
349 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
350 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
356 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
357 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
H A DImplicitNullChecks.cpp621 unsigned DefReg = NoRegister; in insertFaultingInstr() local
623 DefReg = MI->getOperand(0).getReg(); in insertFaultingInstr()
634 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg) in insertFaultingInstr()
H A DMachineSink.cpp1019 for (auto DefReg : DefedRegsInCopy) { in getSingleLiveInSuccBB() local
1021 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI); in getSingleLiveInSuccBB()
1054 for (unsigned DefReg : DefedRegsInCopy) in updateLiveIn() local
1055 for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S) in updateLiveIn()
H A DLiveVariables.cpp218 unsigned DefReg = MO.getReg(); in FindLastPartialDef() local
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef()
H A DTargetInstrInfo.cpp882 unsigned DefReg = MI.getOperand(0).getReg(); in isReallyTriviallyReMaterializableGeneric() local
888 if (TargetRegisterInfo::isVirtualRegister(DefReg) && in isReallyTriviallyReMaterializableGeneric()
889 MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric()
939 if (MO.isDef() && Reg != DefReg) in isReallyTriviallyReMaterializableGeneric()
H A DPHIElimination.cpp172 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction() local
173 if (MRI->use_nodbg_empty(DefReg)) { in runOnMachineFunction()
H A DTwoAddressInstructionPass.cpp228 unsigned DefReg = 0; in sink3AddrInstruction() local
244 if (DefReg) in sink3AddrInstruction()
247 DefReg = MO.getReg(); in sink3AddrInstruction()
306 if (DefReg == MOReg) in sink3AddrInstruction()
H A DMachineVerifier.cpp1830 unsigned DefReg = MODef.getReg(); in checkPHIOps() local
1831 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in checkPHIOps()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp428 unsigned DefReg = MO.getReg(); in OneUseDominatesOtherUses() local
429 if (!TargetRegisterInfo::isVirtualRegister(DefReg) || in OneUseDominatesOtherUses()
430 !MFI.isVRegStackified(DefReg)) in OneUseDominatesOtherUses()
432 assert(MRI.hasOneNonDBGUse(DefReg)); in OneUseDominatesOtherUses()
433 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg); in OneUseDominatesOtherUses()
600 unsigned DefReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse() local
605 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in MoveAndTeeForMultiUse()
607 DefMO.setReg(DefReg); in MoveAndTeeForMultiUse()
623 LIS.createAndComputeVirtRegInterval(DefReg); in MoveAndTeeForMultiUse()
624 MFI.stackifyVReg(DefReg); in MoveAndTeeForMultiUse()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp731 const LLT DefTy = MRI.getType(DefReg); in select()
735 DefRC = TRI.getRegClass(DefReg); in select()
738 MRI.getRegClassOrRegBank(DefReg); in select()
837 const unsigned DefReg = I.getOperand(0).getReg(); in select() local
838 const LLT DefTy = MRI.getType(DefReg); in select()
896 .addDef(DefReg) in select()
1110 const unsigned DefReg = I.getOperand(0).getReg(); in select() local
1315 .addDef(DefReg) in select()
1322 .addDef(DefReg) in select()
1481 unsigned Def1Reg = DefReg; in select()
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H A DAArch64RedundantCopyElimination.cpp383 MCPhysReg DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
386 if (!MRI->isReserved(DefReg) && in optimizeBlock()
390 if (KnownReg.Reg != DefReg && in optimizeBlock()
391 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp512 const unsigned DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local
513 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
538 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
561 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
614 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
633 LLT Ty = MRI.getType(DefReg); in selectConstant()
854 unsigned DefReg = SrcReg; in selectZext() local
866 .addReg(DefReg) in selectZext()
1369 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1383 DefReg = Tmp; in selectMergeValues()
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H A DX86DomainReassignment.cpp598 unsigned DefReg = DefOp.getReg(); in buildClosure() local
599 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) { in buildClosure()
603 visitRegister(C, DefReg, Domain, Worklist); in buildClosure()
H A DX86SpeculativeLoadHardening.cpp2150 unsigned DefReg = MI.getOperand(0).getReg(); in sinkPostLoadHardenedInst() local
2156 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) { in sinkPostLoadHardenedInst()
2181 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) || in sinkPostLoadHardenedInst()
2182 (IndexMO.isReg() && IndexMO.getReg() == DefReg)) in sinkPostLoadHardenedInst()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp674 unsigned DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
680 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
704 unsigned DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
723 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
763 unsigned DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
765 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
H A DPPCMIPeephole.cpp316 unsigned DefReg = in simplifyCode() local
318 if (TargetRegisterInfo::isVirtualRegister(DefReg)) { in simplifyCode()
319 MachineInstr *LoadMI = MRI->getVRegDef(DefReg); in simplifyCode()
H A DPPCInstrInfo.cpp2494 unsigned DefReg = MI.getOperand(0).getReg(); in convertToImmediateForm() local
2499 for (auto &CompareUseMI : MRI->use_instructions(DefReg)) { in convertToImmediateForm()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp374 int DefReg = 0; in loadImmediate() local
378 DefReg = MO.getReg(); in loadImmediate()
397 if (DefReg != Reg) { in loadImmediate()
412 if (DefReg!= SpReg) { in loadImmediate()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp206 unsigned DefReg = findSinkableLocalRegDef(LocalMI); in flushLocalValueMap() local
207 if (DefReg == 0) in flushLocalValueMap()
210 sinkLocalValueMaterialization(LocalMI, DefReg, OrderMap); in flushLocalValueMap()
221 static bool isRegUsedByPhiNodes(unsigned DefReg, in isRegUsedByPhiNodes() argument
224 if (P.second == DefReg) in isRegUsedByPhiNodes()
250 unsigned DefReg, in sinkLocalValueMaterialization() argument
257 if (FuncInfo.RegsWithFixups.count(DefReg)) in sinkLocalValueMaterialization()
262 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo); in sinkLocalValueMaterialization()
263 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { in sinkLocalValueMaterialization()
281 for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) { in sinkLocalValueMaterialization()
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/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp96 bool checkLoadDef(unsigned DefReg, unsigned match_load_op);
639 bool BPFDAGToDAGISel::checkLoadDef(unsigned DefReg, unsigned match_load_op) { in checkLoadDef() argument
640 auto it = load_to_vreg_.find(DefReg); in checkLoadDef()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp217 unsigned DefReg = MODef.getReg(); in eraseInstrWithNoUses() local
218 if (!TRI->isVirtualRegister(DefReg)) { in eraseInstrWithNoUses()
H A DARMLoadStoreOptimizer.cpp871 unsigned DefReg = MO.getReg(); in MergeOpsUpdate() local
873 if (is_contained(ImpDefs, DefReg)) in MergeOpsUpdate()
876 if (MI->readsRegister(DefReg)) in MergeOpsUpdate()
878 ImpDefs.push_back(DefReg); in MergeOpsUpdate()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp1042 unsigned DefReg = 0; in getUniqueDefVReg() local
1049 if (DefReg != 0) in getUniqueDefVReg()
1051 DefReg = R; in getUniqueDefVReg()
1053 return DefReg; in getUniqueDefVReg()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DFastISel.h582 void sinkLocalValueMaterialization(MachineInstr &LocalMI, unsigned DefReg,