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Searched refs:write_reg (Results 1 – 25 of 31) sorted by relevance

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/dpdk/drivers/net/ngbe/base/
H A Dngbe_phy_rtl.c48 hw->phy.write_reg(hw, RTL_LCR, 0xd04, value); in ngbe_phy_led_ctrl_rtl()
49 hw->phy.write_reg(hw, RTL_EEELCR, 0xd04, 0); in ngbe_phy_led_ctrl_rtl()
60 hw->phy.write_reg(hw, RTL_LPCR, 0xd04, value); in ngbe_phy_led_ctrl_rtl()
70 hw->phy.write_reg(hw, RTL_INER, 0xa42, value); in ngbe_init_phy_rtl()
86 hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EFUSE); in ngbe_init_phy_rtl()
199 hw->phy.write_reg(hw, RTL_GBCR, in ngbe_setup_phy_link_rtl()
205 hw->phy.write_reg(hw, RTL_GBCR, in ngbe_setup_phy_link_rtl()
214 hw->phy.write_reg(hw, RTL_ANAR, in ngbe_setup_phy_link_rtl()
220 hw->phy.write_reg(hw, RTL_ANAR, in ngbe_setup_phy_link_rtl()
229 hw->phy.write_reg(hw, RTL_ANAR, in ngbe_setup_phy_link_rtl()
[all …]
H A Dngbe_phy_yt.c114 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_init_phy_yt()
159 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_setup_phy_link_yt()
168 hw->phy.write_reg(hw, YT_ANA, 0, value); in ngbe_setup_phy_link_yt()
196 hw->phy.write_reg(hw, YT_ANA, 0, value); in ngbe_setup_phy_link_yt()
201 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_setup_phy_link_yt()
227 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_setup_phy_link_yt()
236 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_setup_phy_link_yt()
248 hw->phy.write_reg(hw, YT_ANA, 0, value); in ngbe_setup_phy_link_yt()
279 hw->phy.write_reg(hw, YT_ANA, 0, value); in ngbe_setup_phy_link_yt()
286 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_setup_phy_link_yt()
[all …]
H A Dngbe_phy_mvl.c89 hw->phy.write_reg(hw, MVL_CTRL, 0, MVL_CTRL_RESET); in ngbe_init_phy_mvl()
122 hw->phy.write_reg(hw, MVL_INTR_EN, 0, value); in ngbe_init_phy_mvl()
200 hw->phy.write_reg(hw, MVL_ANA, 0, value_r4); in ngbe_setup_phy_link_mvl()
206 hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9); in ngbe_setup_phy_link_mvl()
213 hw->phy.write_reg(hw, MVL_ANA, 0, value); in ngbe_setup_phy_link_mvl()
316 status = hw->phy.write_reg(hw, MVL_ANA, 0, value); in ngbe_set_phy_pause_adv_mvl()
H A Dngbe_dummy.h331 hw->phy.write_reg = ngbe_phy_write_reg_dummy; in ngbe_init_ops_dummy()
H A Dngbe_type.h348 s32 (*write_reg)(struct ngbe_hw *hw, u32 reg_addr, member
/dpdk/drivers/net/e1000/base/
H A De1000_82541.c75 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82541()
680 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
711 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
741 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
755 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
798 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
808 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
954 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_82541()
967 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_82541()
1150 hw->phy.ops.write_reg(hw, in e1000_phy_init_script_82541()
[all …]
H A De1000_phy.c63 phy->ops.write_reg = e1000_null_write_reg; in e1000_init_phy_ops_generic()
248 if (!hw->phy.ops.write_reg) in e1000_phy_reset_dsp_generic()
1422 ret_val = phy->ops.write_reg(hw, in e1000_copper_link_setup_igp()
1865 ret_val = phy->ops.write_reg(hw, in e1000_phy_force_speed_duplex_m88()
2094 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_generic()
2107 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_generic()
2897 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); in e1000_phy_init_script_igp3()
2899 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); in e1000_phy_init_script_igp3()
2901 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); in e1000_phy_init_script_igp3()
2903 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); in e1000_phy_init_script_igp3()
[all …]
H A De1000_82575.c173 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; in e1000_init_phy_params_82575()
180 phy->ops.write_reg = e1000_write_phy_reg_82580; in e1000_init_phy_params_82575()
185 phy->ops.write_reg = e1000_write_phy_reg_gs40g; in e1000_init_phy_params_82575()
189 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82575()
703 if (!(hw->phy.ops.write_reg)) in e1000_phy_hw_reset_sgmii_82575()
710 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); in e1000_phy_hw_reset_sgmii_82575()
754 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
769 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
785 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82575()
798 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82575()
[all …]
H A De1000_82540.c54 phy->ops.write_reg = e1000_write_phy_reg_m88; in e1000_init_phy_params_82540()
405 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_setup_copper_link_82540()
483 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL, in e1000_adjust_serdes_amplitude_82540()
514 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); in e1000_set_vco_speed_82540()
523 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); in e1000_set_vco_speed_82540()
529 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); in e1000_set_vco_speed_82540()
538 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); in e1000_set_vco_speed_82540()
542 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_vco_speed_82540()
575 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_phy_mode_82540()
581 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, in e1000_set_phy_mode_82540()
H A De1000_80003es2lan.c92 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; in e1000_init_phy_params_80003es2lan()
651 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
666 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
714 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
1028 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1068 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1101 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1120 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1131 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1145 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
[all …]
H A De1000_82543.c84 phy->ops.write_reg = (hw->mac.type == e1000_82543) in e1000_init_phy_params_82543()
740 if (!(hw->phy.ops.write_reg)) in e1000_polarity_reversal_workaround_82543()
747 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); in e1000_polarity_reversal_workaround_82543()
750 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); in e1000_polarity_reversal_workaround_82543()
754 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); in e1000_polarity_reversal_workaround_82543()
786 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); in e1000_polarity_reversal_workaround_82543()
790 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); in e1000_polarity_reversal_workaround_82543()
794 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); in e1000_polarity_reversal_workaround_82543()
798 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); in e1000_polarity_reversal_workaround_82543()
802 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); in e1000_polarity_reversal_workaround_82543()
H A De1000_ich8lan.c441 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
532 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_ich8lan()
541 phy->ops.write_reg = e1000_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
3179 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3204 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3217 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3272 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3285 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3314 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
5218 ret_val = hw->phy.ops.write_reg(hw, in e1000_setup_link_ich8lan()
[all …]
H A De1000_82571.c97 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82571()
110 phy->ops.write_reg = e1000_write_phy_reg_m88; in e1000_init_phy_params_82571()
126 phy->ops.write_reg = e1000_write_phy_reg_bm2; in e1000_init_phy_params_82571()
973 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82571()
984 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82571()
990 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82571()
1005 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82571()
1018 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82571()
H A De1000_api.c975 if (hw->phy.ops.write_reg) in e1000_write_phy_reg()
976 return hw->phy.ops.write_reg(hw, offset, data); in e1000_write_phy_reg()
H A De1000_hw.h738 s32 (*write_reg)(struct e1000_hw *, u32, u16); member
/dpdk/drivers/net/igc/base/
H A Digc_phy.c63 phy->ops.write_reg = igc_null_write_reg; in igc_init_phy_ops_generic()
247 if (!hw->phy.ops.write_reg) in igc_phy_reset_dsp_generic()
1420 ret_val = phy->ops.write_reg(hw, in igc_copper_link_setup_igp()
1620 ret_val = phy->ops.write_reg(hw, in igc_phy_setup_autoneg()
1899 ret_val = phy->ops.write_reg(hw, in igc_phy_force_speed_duplex_m88()
2129 ret_val = phy->ops.write_reg(hw, in igc_set_d3_lplu_state_generic()
2142 ret_val = phy->ops.write_reg(hw, in igc_set_d3_lplu_state_generic()
2937 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); in igc_phy_init_script_igp3()
2939 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); in igc_phy_init_script_igp3()
2941 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); in igc_phy_init_script_igp3()
[all …]
H A Digc_api.c1456 if (hw->phy.ops.write_reg) in igc_write_phy_reg()
1457 return hw->phy.ops.write_reg(hw, offset, data); in igc_write_phy_reg()
H A Digc_hw.h750 s32 (*write_reg)(struct igc_hw *hw, u32 offset, u16 data); member
H A Digc_i225.c173 phy->ops.write_reg = igc_write_phy_reg_gpy; in igc_init_phy_params_i225()
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_phy.c227 phy->ops.write_reg = ixgbe_write_phy_reg_generic; in ixgbe_init_phy_ops_generic()
492 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, in ixgbe_reset_phy_generic()
556 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, in ixgbe_restart_auto_neg()
796 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, in ixgbe_setup_phy_link_generic()
825 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, in ixgbe_setup_phy_link_generic()
840 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, in ixgbe_setup_phy_link_generic()
1029 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, in ixgbe_setup_phy_link_tnx()
1044 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, in ixgbe_setup_phy_link_tnx()
1059 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, in ixgbe_setup_phy_link_tnx()
1129 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, in ixgbe_reset_phy_nl()
[all …]
H A Dixgbe_x550.c474 hw->phy.ops.write_reg = NULL; in ixgbe_identify_phy_fw()
2052 status = hw->phy.ops.write_reg(hw, in ixgbe_enable_lasi_ext_t_x550em()
2071 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, in ixgbe_enable_lasi_ext_t_x550em()
2089 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, in ixgbe_enable_lasi_ext_t_x550em()
2272 hw->phy.ops.write_reg = NULL; in ixgbe_init_phy_ops_X550em()
2283 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; in ixgbe_init_phy_ops_X550em()
2316 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
2321 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
2332 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
2563 status = hw->phy.ops.write_reg(hw, in ixgbe_init_ext_t_x550em()
[all …]
H A Dixgbe_api.c552 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, in ixgbe_write_phy_reg()
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.c240 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL, in txgbe_reset_extphy()
451 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, in txgbe_setup_phy_link()
477 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, in txgbe_setup_phy_link()
492 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, in txgbe_setup_phy_link()
506 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, in txgbe_setup_phy_link()
688 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, in txgbe_setup_phy_link_tnx()
703 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG, in txgbe_setup_phy_link_tnx()
718 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, in txgbe_setup_phy_link_tnx()
733 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, in txgbe_setup_phy_link_tnx()
H A Dtxgbe_dummy.h630 hw->phy.write_reg = txgbe_phy_write_reg_dummy; in txgbe_init_ops_dummy()
H A Dtxgbe_type.h644 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr, member

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