1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
4 */
5
6 #include "txgbe_hw.h"
7 #include "txgbe_eeprom.h"
8 #include "txgbe_mng.h"
9 #include "txgbe_phy.h"
10
11 static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr);
12 static void txgbe_i2c_stop(struct txgbe_hw *hw);
13 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw);
14 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
15 u32 link_partner, struct txgbe_hw *hw);
16 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability,
17 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw);
18 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw);
19 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw);
20 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode);
21 static s32 txgbe_check_kr_training(struct txgbe_hw *hw);
22 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw,
23 s32 post, s32 mode);
24 static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed);
25
26 /**
27 * txgbe_identify_extphy - Identify a single address for a PHY
28 * @hw: pointer to hardware structure
29 * @phy_addr: PHY address to probe
30 *
31 * Returns true if PHY found
32 */
txgbe_identify_extphy(struct txgbe_hw * hw)33 static bool txgbe_identify_extphy(struct txgbe_hw *hw)
34 {
35 u16 phy_addr = 0;
36
37 if (!txgbe_validate_phy_addr(hw, phy_addr)) {
38 DEBUGOUT("Unable to validate PHY address 0x%04X",
39 phy_addr);
40 return false;
41 }
42
43 if (txgbe_get_phy_id(hw))
44 return false;
45
46 hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id);
47 if (hw->phy.type == txgbe_phy_unknown) {
48 u16 ext_ability = 0;
49 hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY,
50 TXGBE_MD_DEV_PMA_PMD,
51 &ext_ability);
52
53 if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY |
54 TXGBE_MD_PHY_1000BASET_ABILITY))
55 hw->phy.type = txgbe_phy_cu_unknown;
56 else
57 hw->phy.type = txgbe_phy_generic;
58 }
59
60 return true;
61 }
62
63 /**
64 * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register
65 * @hw: pointer to hardware structure
66 *
67 * Read TXGBE_ETHPHYIF register and save field values,
68 * and check for valid field values.
69 **/
txgbe_read_phy_if(struct txgbe_hw * hw)70 static s32 txgbe_read_phy_if(struct txgbe_hw *hw)
71 {
72 hw->phy.media_type = hw->phy.get_media_type(hw);
73
74 /* Save NW management interface connected on board. This is used
75 * to determine internal PHY mode.
76 */
77 hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF);
78
79 /* If MDIO is connected to external PHY, then set PHY address. */
80 if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT)
81 hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel);
82
83 if (!hw->phy.phy_semaphore_mask) {
84 if (hw->bus.lan_id)
85 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
86 else
87 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
88 }
89
90 return 0;
91 }
92
93 /**
94 * txgbe_identify_phy - Get physical layer module
95 * @hw: pointer to hardware structure
96 *
97 * Determines the physical layer module found on the current adapter.
98 **/
txgbe_identify_phy(struct txgbe_hw * hw)99 s32 txgbe_identify_phy(struct txgbe_hw *hw)
100 {
101 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
102
103 txgbe_read_phy_if(hw);
104
105 if (hw->phy.type != txgbe_phy_unknown)
106 return 0;
107
108 /* Raptor 10GBASE-T requires an external PHY */
109 if (hw->phy.media_type == txgbe_media_type_copper) {
110 err = txgbe_identify_extphy(hw);
111 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
112 err = txgbe_identify_module(hw);
113 } else {
114 hw->phy.type = txgbe_phy_none;
115 return 0;
116 }
117
118 /* Return error if SFP module has been detected but is not supported */
119 if (hw->phy.type == txgbe_phy_sfp_unsupported)
120 return TXGBE_ERR_SFP_NOT_SUPPORTED;
121
122 return err;
123 }
124
125 /**
126 * txgbe_check_reset_blocked - check status of MNG FW veto bit
127 * @hw: pointer to the hardware structure
128 *
129 * This function checks the STAT.MNGVETO bit to see if there are
130 * any constraints on link from manageability. For MAC's that don't
131 * have this bit just return faluse since the link can not be blocked
132 * via this method.
133 **/
txgbe_check_reset_blocked(struct txgbe_hw * hw)134 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw)
135 {
136 u32 mmngc;
137
138 mmngc = rd32(hw, TXGBE_STAT);
139 if (mmngc & TXGBE_STAT_MNGVETO) {
140 DEBUGOUT("MNG_VETO bit detected.");
141 return true;
142 }
143
144 return false;
145 }
146
147 /**
148 * txgbe_validate_phy_addr - Determines phy address is valid
149 * @hw: pointer to hardware structure
150 * @phy_addr: PHY address
151 *
152 **/
txgbe_validate_phy_addr(struct txgbe_hw * hw,u32 phy_addr)153 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr)
154 {
155 u16 phy_id = 0;
156 bool valid = false;
157
158 hw->phy.addr = phy_addr;
159 hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
160 TXGBE_MD_DEV_PMA_PMD, &phy_id);
161
162 if (phy_id != 0xFFFF && phy_id != 0x0)
163 valid = true;
164
165 DEBUGOUT("PHY ID HIGH is 0x%04X", phy_id);
166
167 return valid;
168 }
169
170 /**
171 * txgbe_get_phy_id - Get the phy type
172 * @hw: pointer to hardware structure
173 *
174 **/
txgbe_get_phy_id(struct txgbe_hw * hw)175 s32 txgbe_get_phy_id(struct txgbe_hw *hw)
176 {
177 u32 err;
178 u16 phy_id_high = 0;
179 u16 phy_id_low = 0;
180
181 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
182 TXGBE_MD_DEV_PMA_PMD,
183 &phy_id_high);
184
185 if (err == 0) {
186 hw->phy.id = (u32)(phy_id_high << 16);
187 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW,
188 TXGBE_MD_DEV_PMA_PMD,
189 &phy_id_low);
190 hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK);
191 hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK);
192 }
193 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X",
194 phy_id_high, phy_id_low);
195
196 return err;
197 }
198
199 /**
200 * txgbe_get_phy_type_from_id - Get the phy type
201 * @phy_id: PHY ID information
202 *
203 **/
txgbe_get_phy_type_from_id(u32 phy_id)204 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id)
205 {
206 enum txgbe_phy_type phy_type;
207
208 switch (phy_id) {
209 case TXGBE_PHYID_TN1010:
210 phy_type = txgbe_phy_tn;
211 break;
212 case TXGBE_PHYID_QT2022:
213 phy_type = txgbe_phy_qt;
214 break;
215 case TXGBE_PHYID_ATH:
216 phy_type = txgbe_phy_nl;
217 break;
218 case TXGBE_PHYID_MTD3310:
219 phy_type = txgbe_phy_cu_mtd;
220 break;
221 default:
222 phy_type = txgbe_phy_unknown;
223 break;
224 }
225
226 return phy_type;
227 }
228
229 static s32
txgbe_reset_extphy(struct txgbe_hw * hw)230 txgbe_reset_extphy(struct txgbe_hw *hw)
231 {
232 u16 ctrl = 0;
233 int err, i;
234
235 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
236 TXGBE_MD_DEV_GENERAL, &ctrl);
237 if (err != 0)
238 return err;
239 ctrl |= TXGBE_MD_PORT_CTRL_RESET;
240 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL,
241 TXGBE_MD_DEV_GENERAL, ctrl);
242 if (err != 0)
243 return err;
244
245 /*
246 * Poll for reset bit to self-clear indicating reset is complete.
247 * Some PHYs could take up to 3 seconds to complete and need about
248 * 1.7 usec delay after the reset is complete.
249 */
250 for (i = 0; i < 30; i++) {
251 msec_delay(100);
252 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
253 TXGBE_MD_DEV_GENERAL, &ctrl);
254 if (err != 0)
255 return err;
256
257 if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) {
258 usec_delay(2);
259 break;
260 }
261 }
262
263 if (ctrl & TXGBE_MD_PORT_CTRL_RESET) {
264 err = TXGBE_ERR_RESET_FAILED;
265 DEBUGOUT("PHY reset polling failed to complete.");
266 }
267
268 return err;
269 }
270
271 /**
272 * txgbe_reset_phy - Performs a PHY reset
273 * @hw: pointer to hardware structure
274 **/
txgbe_reset_phy(struct txgbe_hw * hw)275 s32 txgbe_reset_phy(struct txgbe_hw *hw)
276 {
277 s32 err = 0;
278
279 if (hw->phy.type == txgbe_phy_unknown)
280 err = txgbe_identify_phy(hw);
281
282 if (err != 0 || hw->phy.type == txgbe_phy_none)
283 return err;
284
285 /* Don't reset PHY if it's shut down due to overtemp. */
286 if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP)
287 return err;
288
289 /* Blocked by MNG FW so bail */
290 if (txgbe_check_reset_blocked(hw))
291 return err;
292
293 switch (hw->phy.type) {
294 case txgbe_phy_cu_mtd:
295 err = txgbe_reset_extphy(hw);
296 break;
297 default:
298 break;
299 }
300
301 return err;
302 }
303
304 /**
305 * txgbe_read_phy_mdi - Reads a value from a specified PHY register without
306 * the SWFW lock
307 * @hw: pointer to hardware structure
308 * @reg_addr: 32 bit address of PHY register to read
309 * @device_type: 5 bit device type
310 * @phy_data: Pointer to read data from PHY register
311 **/
txgbe_read_phy_reg_mdi(struct txgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)312 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
313 u16 *phy_data)
314 {
315 u32 command, data;
316
317 /* Setup and write the address cycle command */
318 command = TXGBE_MDIOSCA_REG(reg_addr) |
319 TXGBE_MDIOSCA_DEV(device_type) |
320 TXGBE_MDIOSCA_PORT(hw->phy.addr);
321 wr32(hw, TXGBE_MDIOSCA, command);
322
323 command = TXGBE_MDIOSCD_CMD_READ |
324 TXGBE_MDIOSCD_BUSY;
325 wr32(hw, TXGBE_MDIOSCD, command);
326
327 /*
328 * Check every 10 usec to see if the address cycle completed.
329 * The MDI Command bit will clear when the operation is
330 * complete
331 */
332 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
333 0, NULL, 100, 100)) {
334 DEBUGOUT("PHY address command did not complete");
335 return TXGBE_ERR_PHY;
336 }
337
338 data = rd32(hw, TXGBE_MDIOSCD);
339 *phy_data = (u16)TXGBD_MDIOSCD_DAT(data);
340
341 return 0;
342 }
343
344 /**
345 * txgbe_read_phy_reg - Reads a value from a specified PHY register
346 * using the SWFW lock - this function is needed in most cases
347 * @hw: pointer to hardware structure
348 * @reg_addr: 32 bit address of PHY register to read
349 * @device_type: 5 bit device type
350 * @phy_data: Pointer to read data from PHY register
351 **/
txgbe_read_phy_reg(struct txgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)352 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
353 u32 device_type, u16 *phy_data)
354 {
355 s32 err;
356 u32 gssr = hw->phy.phy_semaphore_mask;
357
358 if (hw->mac.acquire_swfw_sync(hw, gssr))
359 return TXGBE_ERR_SWFW_SYNC;
360
361 err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data);
362
363 hw->mac.release_swfw_sync(hw, gssr);
364
365 return err;
366 }
367
368 /**
369 * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register
370 * without SWFW lock
371 * @hw: pointer to hardware structure
372 * @reg_addr: 32 bit PHY register to write
373 * @device_type: 5 bit device type
374 * @phy_data: Data to write to the PHY register
375 **/
txgbe_write_phy_reg_mdi(struct txgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)376 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr,
377 u32 device_type, u16 phy_data)
378 {
379 u32 command;
380
381 /* write command */
382 command = TXGBE_MDIOSCA_REG(reg_addr) |
383 TXGBE_MDIOSCA_DEV(device_type) |
384 TXGBE_MDIOSCA_PORT(hw->phy.addr);
385 wr32(hw, TXGBE_MDIOSCA, command);
386
387 command = TXGBE_MDIOSCD_CMD_WRITE |
388 TXGBE_MDIOSCD_DAT(phy_data) |
389 TXGBE_MDIOSCD_BUSY;
390 wr32(hw, TXGBE_MDIOSCD, command);
391
392 /* wait for completion */
393 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
394 0, NULL, 100, 100)) {
395 DEBUGOUT("PHY write cmd didn't complete");
396 return -TERR_PHY;
397 }
398
399 return 0;
400 }
401
402 /**
403 * txgbe_write_phy_reg - Writes a value to specified PHY register
404 * using SWFW lock- this function is needed in most cases
405 * @hw: pointer to hardware structure
406 * @reg_addr: 32 bit PHY register to write
407 * @device_type: 5 bit device type
408 * @phy_data: Data to write to the PHY register
409 **/
txgbe_write_phy_reg(struct txgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)410 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
411 u32 device_type, u16 phy_data)
412 {
413 s32 err;
414 u32 gssr = hw->phy.phy_semaphore_mask;
415
416 if (hw->mac.acquire_swfw_sync(hw, gssr))
417 err = TXGBE_ERR_SWFW_SYNC;
418
419 err = hw->phy.write_reg_mdi(hw, reg_addr, device_type,
420 phy_data);
421 hw->mac.release_swfw_sync(hw, gssr);
422
423 return err;
424 }
425
426 /**
427 * txgbe_setup_phy_link - Set and restart auto-neg
428 * @hw: pointer to hardware structure
429 *
430 * Restart auto-negotiation and PHY and waits for completion.
431 **/
txgbe_setup_phy_link(struct txgbe_hw * hw)432 s32 txgbe_setup_phy_link(struct txgbe_hw *hw)
433 {
434 s32 err = 0;
435 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
436 bool autoneg = false;
437 u32 speed;
438
439 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
440
441 /* Set or unset auto-negotiation 10G advertisement */
442 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
443 TXGBE_MD_DEV_AUTO_NEG,
444 &autoneg_reg);
445
446 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
447 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) &&
448 (speed & TXGBE_LINK_SPEED_10GB_FULL))
449 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
450
451 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
452 TXGBE_MD_DEV_AUTO_NEG,
453 autoneg_reg);
454
455 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
456 TXGBE_MD_DEV_AUTO_NEG,
457 &autoneg_reg);
458
459 /* Set or unset auto-negotiation 5G advertisement */
460 autoneg_reg &= ~TXGBE_MII_5GBASE_T_ADVERTISE;
461 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_5GB_FULL) &&
462 (speed & TXGBE_LINK_SPEED_5GB_FULL))
463 autoneg_reg |= TXGBE_MII_5GBASE_T_ADVERTISE;
464
465 /* Set or unset auto-negotiation 2.5G advertisement */
466 autoneg_reg &= ~TXGBE_MII_2_5GBASE_T_ADVERTISE;
467 if ((hw->phy.autoneg_advertised &
468 TXGBE_LINK_SPEED_2_5GB_FULL) &&
469 (speed & TXGBE_LINK_SPEED_2_5GB_FULL))
470 autoneg_reg |= TXGBE_MII_2_5GBASE_T_ADVERTISE;
471 /* Set or unset auto-negotiation 1G advertisement */
472 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE;
473 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) &&
474 (speed & TXGBE_LINK_SPEED_1GB_FULL))
475 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE;
476
477 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
478 TXGBE_MD_DEV_AUTO_NEG,
479 autoneg_reg);
480
481 /* Set or unset auto-negotiation 100M advertisement */
482 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
483 TXGBE_MD_DEV_AUTO_NEG,
484 &autoneg_reg);
485
486 autoneg_reg &= ~(TXGBE_MII_100BASE_T_ADVERTISE |
487 TXGBE_MII_100BASE_T_ADVERTISE_HALF);
488 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) &&
489 (speed & TXGBE_LINK_SPEED_100M_FULL))
490 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
491
492 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
493 TXGBE_MD_DEV_AUTO_NEG,
494 autoneg_reg);
495
496 /* Blocked by MNG FW so don't reset PHY */
497 if (txgbe_check_reset_blocked(hw))
498 return err;
499
500 /* Restart PHY auto-negotiation. */
501 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
502 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
503
504 autoneg_reg |= TXGBE_MII_RESTART;
505
506 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
507 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
508
509 return err;
510 }
511
512 /**
513 * txgbe_setup_phy_link_speed - Sets the auto advertised capabilities
514 * @hw: pointer to hardware structure
515 * @speed: new link speed
516 * @autoneg_wait_to_complete: unused
517 **/
txgbe_setup_phy_link_speed(struct txgbe_hw * hw,u32 speed,bool autoneg_wait_to_complete)518 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
519 u32 speed,
520 bool autoneg_wait_to_complete)
521 {
522 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
523
524 /*
525 * Clear autoneg_advertised and set new values based on input link
526 * speed.
527 */
528 hw->phy.autoneg_advertised = 0;
529
530 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
531 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
532
533 if (speed & TXGBE_LINK_SPEED_5GB_FULL)
534 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_5GB_FULL;
535
536 if (speed & TXGBE_LINK_SPEED_2_5GB_FULL)
537 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_2_5GB_FULL;
538
539 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
540 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
541
542 if (speed & TXGBE_LINK_SPEED_100M_FULL)
543 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
544
545 if (speed & TXGBE_LINK_SPEED_10M_FULL)
546 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10M_FULL;
547
548 /* Setup link based on the new speed settings */
549 hw->phy.setup_link(hw);
550
551 return 0;
552 }
553
txgbe_get_phy_fw_version(struct txgbe_hw * hw,u32 * fw_version)554 s32 txgbe_get_phy_fw_version(struct txgbe_hw *hw, u32 *fw_version)
555 {
556 u16 eeprom_verh, eeprom_verl;
557
558 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
559 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
560
561 *fw_version = (eeprom_verh << 16) | eeprom_verl;
562
563 return 0;
564 }
565
566 /**
567 * txgbe_get_copper_speeds_supported - Get copper link speeds from phy
568 * @hw: pointer to hardware structure
569 *
570 * Determines the supported link capabilities by reading the PHY auto
571 * negotiation register.
572 **/
txgbe_get_copper_speeds_supported(struct txgbe_hw * hw)573 static s32 txgbe_get_copper_speeds_supported(struct txgbe_hw *hw)
574 {
575 s32 err;
576 u16 speed_ability;
577
578 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_SPEED_ABILITY,
579 TXGBE_MD_DEV_PMA_PMD,
580 &speed_ability);
581 if (err)
582 return err;
583
584 if (speed_ability & TXGBE_MD_PHY_SPEED_10G)
585 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_10GB_FULL;
586 if (speed_ability & TXGBE_MD_PHY_SPEED_1G)
587 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_1GB_FULL;
588 if (speed_ability & TXGBE_MD_PHY_SPEED_100M)
589 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_100M_FULL;
590
591 return err;
592 }
593
594 /**
595 * txgbe_get_copper_link_capabilities - Determines link capabilities
596 * @hw: pointer to hardware structure
597 * @speed: pointer to link speed
598 * @autoneg: boolean auto-negotiation value
599 **/
txgbe_get_copper_link_capabilities(struct txgbe_hw * hw,u32 * speed,bool * autoneg)600 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
601 u32 *speed,
602 bool *autoneg)
603 {
604 s32 err = 0;
605
606 *autoneg = true;
607 if (!hw->phy.speeds_supported)
608 err = txgbe_get_copper_speeds_supported(hw);
609
610 *speed = hw->phy.speeds_supported;
611 return err;
612 }
613
614 /**
615 * txgbe_check_phy_link_tnx - Determine link and speed status
616 * @hw: pointer to hardware structure
617 * @speed: current link speed
618 * @link_up: true is link is up, false otherwise
619 *
620 * Reads the VS1 register to determine if link is up and the current speed for
621 * the PHY.
622 **/
txgbe_check_phy_link_tnx(struct txgbe_hw * hw,u32 * speed,bool * link_up)623 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw, u32 *speed,
624 bool *link_up)
625 {
626 s32 err = 0;
627 u32 time_out;
628 u32 max_time_out = 10;
629 u16 phy_link = 0;
630 u16 phy_speed = 0;
631 u16 phy_data = 0;
632
633 /* Initialize speed and link to default case */
634 *link_up = false;
635 *speed = TXGBE_LINK_SPEED_10GB_FULL;
636
637 /*
638 * Check current speed and link status of the PHY register.
639 * This is a vendor specific register and may have to
640 * be changed for other copper PHYs.
641 */
642 for (time_out = 0; time_out < max_time_out; time_out++) {
643 usec_delay(10);
644 err = hw->phy.read_reg(hw,
645 TXGBE_MD_VENDOR_SPECIFIC_1_STATUS,
646 TXGBE_MD_DEV_VENDOR_1,
647 &phy_data);
648 phy_link = phy_data & TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS;
649 phy_speed = phy_data &
650 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS;
651 if (phy_link == TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS) {
652 *link_up = true;
653 if (phy_speed ==
654 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS)
655 *speed = TXGBE_LINK_SPEED_1GB_FULL;
656 break;
657 }
658 }
659
660 return err;
661 }
662
663 /**
664 * txgbe_setup_phy_link_tnx - Set and restart auto-neg
665 * @hw: pointer to hardware structure
666 *
667 * Restart auto-negotiation and PHY and waits for completion.
668 **/
txgbe_setup_phy_link_tnx(struct txgbe_hw * hw)669 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw)
670 {
671 s32 err = 0;
672 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
673 bool autoneg = false;
674 u32 speed;
675
676 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
677
678 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
679 /* Set or unset auto-negotiation 10G advertisement */
680 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
681 TXGBE_MD_DEV_AUTO_NEG,
682 &autoneg_reg);
683
684 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
685 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL)
686 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
687
688 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
689 TXGBE_MD_DEV_AUTO_NEG,
690 autoneg_reg);
691 }
692
693 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
694 /* Set or unset auto-negotiation 1G advertisement */
695 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
696 TXGBE_MD_DEV_AUTO_NEG,
697 &autoneg_reg);
698
699 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
700 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL)
701 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
702
703 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
704 TXGBE_MD_DEV_AUTO_NEG,
705 autoneg_reg);
706 }
707
708 if (speed & TXGBE_LINK_SPEED_100M_FULL) {
709 /* Set or unset auto-negotiation 100M advertisement */
710 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
711 TXGBE_MD_DEV_AUTO_NEG,
712 &autoneg_reg);
713
714 autoneg_reg &= ~TXGBE_MII_100BASE_T_ADVERTISE;
715 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL)
716 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
717
718 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
719 TXGBE_MD_DEV_AUTO_NEG,
720 autoneg_reg);
721 }
722
723 /* Blocked by MNG FW so don't reset PHY */
724 if (txgbe_check_reset_blocked(hw))
725 return err;
726
727 /* Restart PHY auto-negotiation. */
728 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
729 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
730
731 autoneg_reg |= TXGBE_MII_RESTART;
732
733 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
734 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
735
736 return err;
737 }
738
739 /**
740 * txgbe_identify_module - Identifies module type
741 * @hw: pointer to hardware structure
742 *
743 * Determines HW type and calls appropriate function.
744 **/
txgbe_identify_module(struct txgbe_hw * hw)745 s32 txgbe_identify_module(struct txgbe_hw *hw)
746 {
747 s32 err = TXGBE_ERR_SFP_NOT_PRESENT;
748
749 switch (hw->phy.media_type) {
750 case txgbe_media_type_fiber:
751 err = txgbe_identify_sfp_module(hw);
752 break;
753
754 case txgbe_media_type_fiber_qsfp:
755 err = txgbe_identify_qsfp_module(hw);
756 break;
757
758 default:
759 hw->phy.sfp_type = txgbe_sfp_type_not_present;
760 err = TXGBE_ERR_SFP_NOT_PRESENT;
761 break;
762 }
763
764 return err;
765 }
766
767 /**
768 * txgbe_identify_sfp_module - Identifies SFP modules
769 * @hw: pointer to hardware structure
770 *
771 * Searches for and identifies the SFP module and assigns appropriate PHY type.
772 **/
txgbe_identify_sfp_module(struct txgbe_hw * hw)773 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
774 {
775 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
776 u32 vendor_oui = 0;
777 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
778 u8 identifier = 0;
779 u8 comp_codes_1g = 0;
780 u8 comp_codes_10g = 0;
781 u8 oui_bytes[3] = {0, 0, 0};
782 u8 cable_tech = 0;
783 u8 cable_spec = 0;
784 u16 enforce_sfp = 0;
785
786 if (hw->phy.media_type != txgbe_media_type_fiber) {
787 hw->phy.sfp_type = txgbe_sfp_type_not_present;
788 return TXGBE_ERR_SFP_NOT_PRESENT;
789 }
790
791 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
792 &identifier);
793 if (err != 0) {
794 ERR_I2C:
795 hw->phy.sfp_type = txgbe_sfp_type_not_present;
796 if (hw->phy.type != txgbe_phy_nl) {
797 hw->phy.id = 0;
798 hw->phy.type = txgbe_phy_unknown;
799 }
800 return TXGBE_ERR_SFP_NOT_PRESENT;
801 }
802
803 if (identifier != TXGBE_SFF_IDENTIFIER_SFP) {
804 hw->phy.type = txgbe_phy_sfp_unsupported;
805 return TXGBE_ERR_SFP_NOT_SUPPORTED;
806 }
807
808 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES,
809 &comp_codes_1g);
810 if (err != 0)
811 goto ERR_I2C;
812
813 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES,
814 &comp_codes_10g);
815 if (err != 0)
816 goto ERR_I2C;
817
818 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY,
819 &cable_tech);
820 if (err != 0)
821 goto ERR_I2C;
822
823 /* ID Module
824 * =========
825 * 0 SFP_DA_CU
826 * 1 SFP_SR
827 * 2 SFP_LR
828 * 3 SFP_DA_CORE0 - chip-specific
829 * 4 SFP_DA_CORE1 - chip-specific
830 * 5 SFP_SR/LR_CORE0 - chip-specific
831 * 6 SFP_SR/LR_CORE1 - chip-specific
832 * 7 SFP_act_lmt_DA_CORE0 - chip-specific
833 * 8 SFP_act_lmt_DA_CORE1 - chip-specific
834 * 9 SFP_1g_cu_CORE0 - chip-specific
835 * 10 SFP_1g_cu_CORE1 - chip-specific
836 * 11 SFP_1g_sx_CORE0 - chip-specific
837 * 12 SFP_1g_sx_CORE1 - chip-specific
838 */
839 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
840 if (hw->bus.lan_id == 0)
841 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
842 else
843 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
844 } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
845 err = hw->phy.read_i2c_eeprom(hw,
846 TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
847 if (err != 0)
848 goto ERR_I2C;
849 if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
850 hw->phy.sfp_type = (hw->bus.lan_id == 0
851 ? txgbe_sfp_type_da_act_lmt_core0
852 : txgbe_sfp_type_da_act_lmt_core1);
853 } else {
854 hw->phy.sfp_type = txgbe_sfp_type_unknown;
855 }
856 } else if (comp_codes_10g &
857 (TXGBE_SFF_10GBASESR_CAPABLE |
858 TXGBE_SFF_10GBASELR_CAPABLE)) {
859 hw->phy.sfp_type = (hw->bus.lan_id == 0
860 ? txgbe_sfp_type_srlr_core0
861 : txgbe_sfp_type_srlr_core1);
862 } else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) {
863 hw->phy.sfp_type = (hw->bus.lan_id == 0
864 ? txgbe_sfp_type_1g_cu_core0
865 : txgbe_sfp_type_1g_cu_core1);
866 } else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) {
867 hw->phy.sfp_type = (hw->bus.lan_id == 0
868 ? txgbe_sfp_type_1g_sx_core0
869 : txgbe_sfp_type_1g_sx_core1);
870 } else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) {
871 hw->phy.sfp_type = (hw->bus.lan_id == 0
872 ? txgbe_sfp_type_1g_lx_core0
873 : txgbe_sfp_type_1g_lx_core1);
874 } else {
875 hw->phy.sfp_type = txgbe_sfp_type_unknown;
876 }
877
878 if (hw->phy.sfp_type != stored_sfp_type)
879 hw->phy.sfp_setup_needed = true;
880
881 /* Determine if the SFP+ PHY is dual speed or not. */
882 hw->phy.multispeed_fiber = false;
883 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
884 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
885 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
886 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
887 hw->phy.multispeed_fiber = true;
888
889 /* Determine PHY vendor */
890 if (hw->phy.type != txgbe_phy_nl) {
891 hw->phy.id = identifier;
892 err = hw->phy.read_i2c_eeprom(hw,
893 TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]);
894 if (err != 0)
895 goto ERR_I2C;
896
897 err = hw->phy.read_i2c_eeprom(hw,
898 TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]);
899 if (err != 0)
900 goto ERR_I2C;
901
902 err = hw->phy.read_i2c_eeprom(hw,
903 TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]);
904 if (err != 0)
905 goto ERR_I2C;
906
907 vendor_oui = ((u32)oui_bytes[0] << 24) |
908 ((u32)oui_bytes[1] << 16) |
909 ((u32)oui_bytes[2] << 8);
910 switch (vendor_oui) {
911 case TXGBE_SFF_VENDOR_OUI_TYCO:
912 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
913 hw->phy.type = txgbe_phy_sfp_tyco_passive;
914 break;
915 case TXGBE_SFF_VENDOR_OUI_FTL:
916 if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
917 hw->phy.type = txgbe_phy_sfp_ftl_active;
918 else
919 hw->phy.type = txgbe_phy_sfp_ftl;
920 break;
921 case TXGBE_SFF_VENDOR_OUI_AVAGO:
922 hw->phy.type = txgbe_phy_sfp_avago;
923 break;
924 case TXGBE_SFF_VENDOR_OUI_INTEL:
925 hw->phy.type = txgbe_phy_sfp_intel;
926 break;
927 default:
928 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
929 hw->phy.type = txgbe_phy_sfp_unknown_passive;
930 else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
931 hw->phy.type = txgbe_phy_sfp_unknown_active;
932 else
933 hw->phy.type = txgbe_phy_sfp_unknown;
934 break;
935 }
936 }
937
938 /* Allow any DA cable vendor */
939 if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE |
940 TXGBE_SFF_CABLE_DA_ACTIVE)) {
941 return 0;
942 }
943
944 /* Verify supported 1G SFP modules */
945 if (comp_codes_10g == 0 &&
946 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
947 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
948 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
949 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
950 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
951 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
952 hw->phy.type = txgbe_phy_sfp_unsupported;
953 return TXGBE_ERR_SFP_NOT_SUPPORTED;
954 }
955
956 hw->mac.get_device_caps(hw, &enforce_sfp);
957 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
958 !hw->allow_unsupported_sfp &&
959 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
960 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
961 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
962 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
963 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
964 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
965 DEBUGOUT("SFP+ module not supported");
966 hw->phy.type = txgbe_phy_sfp_unsupported;
967 return TXGBE_ERR_SFP_NOT_SUPPORTED;
968 }
969
970 return err;
971 }
972
973 /**
974 * txgbe_identify_qsfp_module - Identifies QSFP modules
975 * @hw: pointer to hardware structure
976 *
977 * Searches for and identifies the QSFP module and assigns appropriate PHY type
978 **/
txgbe_identify_qsfp_module(struct txgbe_hw * hw)979 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
980 {
981 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
982 u32 vendor_oui = 0;
983 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
984 u8 identifier = 0;
985 u8 comp_codes_1g = 0;
986 u8 comp_codes_10g = 0;
987 u8 oui_bytes[3] = {0, 0, 0};
988 u16 enforce_sfp = 0;
989 u8 connector = 0;
990 u8 cable_length = 0;
991 u8 device_tech = 0;
992 bool active_cable = false;
993
994 if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
995 hw->phy.sfp_type = txgbe_sfp_type_not_present;
996 err = TXGBE_ERR_SFP_NOT_PRESENT;
997 goto out;
998 }
999
1000 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
1001 &identifier);
1002 ERR_I2C:
1003 if (err != 0) {
1004 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1005 hw->phy.id = 0;
1006 hw->phy.type = txgbe_phy_unknown;
1007 return TXGBE_ERR_SFP_NOT_PRESENT;
1008 }
1009 if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1010 hw->phy.type = txgbe_phy_sfp_unsupported;
1011 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1012 goto out;
1013 }
1014
1015 hw->phy.id = identifier;
1016
1017 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP,
1018 &comp_codes_10g);
1019
1020 if (err != 0)
1021 goto ERR_I2C;
1022
1023 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP,
1024 &comp_codes_1g);
1025
1026 if (err != 0)
1027 goto ERR_I2C;
1028
1029 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1030 hw->phy.type = txgbe_phy_qsfp_unknown_passive;
1031 if (hw->bus.lan_id == 0)
1032 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
1033 else
1034 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
1035 } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1036 TXGBE_SFF_10GBASELR_CAPABLE)) {
1037 if (hw->bus.lan_id == 0)
1038 hw->phy.sfp_type = txgbe_sfp_type_srlr_core0;
1039 else
1040 hw->phy.sfp_type = txgbe_sfp_type_srlr_core1;
1041 } else {
1042 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1043 active_cable = true;
1044
1045 if (!active_cable) {
1046 hw->phy.read_i2c_eeprom(hw,
1047 TXGBE_SFF_QSFP_CONNECTOR,
1048 &connector);
1049
1050 hw->phy.read_i2c_eeprom(hw,
1051 TXGBE_SFF_QSFP_CABLE_LENGTH,
1052 &cable_length);
1053
1054 hw->phy.read_i2c_eeprom(hw,
1055 TXGBE_SFF_QSFP_DEVICE_TECH,
1056 &device_tech);
1057
1058 if (connector ==
1059 TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE &&
1060 cable_length > 0 &&
1061 ((device_tech >> 4) ==
1062 TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL))
1063 active_cable = true;
1064 }
1065
1066 if (active_cable) {
1067 hw->phy.type = txgbe_phy_qsfp_unknown_active;
1068 if (hw->bus.lan_id == 0)
1069 hw->phy.sfp_type =
1070 txgbe_sfp_type_da_act_lmt_core0;
1071 else
1072 hw->phy.sfp_type =
1073 txgbe_sfp_type_da_act_lmt_core1;
1074 } else {
1075 /* unsupported module type */
1076 hw->phy.type = txgbe_phy_sfp_unsupported;
1077 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1078 goto out;
1079 }
1080 }
1081
1082 if (hw->phy.sfp_type != stored_sfp_type)
1083 hw->phy.sfp_setup_needed = true;
1084
1085 /* Determine if the QSFP+ PHY is dual speed or not. */
1086 hw->phy.multispeed_fiber = false;
1087 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
1088 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
1089 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
1090 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
1091 hw->phy.multispeed_fiber = true;
1092
1093 /* Determine PHY vendor for optical modules */
1094 if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1095 TXGBE_SFF_10GBASELR_CAPABLE)) {
1096 err = hw->phy.read_i2c_eeprom(hw,
1097 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1098 &oui_bytes[0]);
1099
1100 if (err != 0)
1101 goto ERR_I2C;
1102
1103 err = hw->phy.read_i2c_eeprom(hw,
1104 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1105 &oui_bytes[1]);
1106
1107 if (err != 0)
1108 goto ERR_I2C;
1109
1110 err = hw->phy.read_i2c_eeprom(hw,
1111 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1112 &oui_bytes[2]);
1113
1114 if (err != 0)
1115 goto ERR_I2C;
1116
1117 vendor_oui =
1118 ((oui_bytes[0] << 24) |
1119 (oui_bytes[1] << 16) |
1120 (oui_bytes[2] << 8));
1121
1122 if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL)
1123 hw->phy.type = txgbe_phy_qsfp_intel;
1124 else
1125 hw->phy.type = txgbe_phy_qsfp_unknown;
1126
1127 hw->mac.get_device_caps(hw, &enforce_sfp);
1128 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1129 /* Make sure we're a supported PHY type */
1130 if (hw->phy.type == txgbe_phy_qsfp_intel) {
1131 err = 0;
1132 } else {
1133 if (hw->allow_unsupported_sfp) {
1134 DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. "
1135 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1136 "Wangxun Corporation is not responsible for any harm caused by using untested modules.");
1137 err = 0;
1138 } else {
1139 DEBUGOUT("QSFP module not supported");
1140 hw->phy.type =
1141 txgbe_phy_sfp_unsupported;
1142 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1143 }
1144 }
1145 } else {
1146 err = 0;
1147 }
1148 }
1149
1150 out:
1151 return err;
1152 }
1153
1154 /**
1155 * txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1156 * @hw: pointer to hardware structure
1157 * @byte_offset: EEPROM byte offset to read
1158 * @eeprom_data: value read
1159 *
1160 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1161 **/
txgbe_read_i2c_eeprom(struct txgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1162 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1163 u8 *eeprom_data)
1164 {
1165 return hw->phy.read_i2c_byte(hw, byte_offset,
1166 TXGBE_I2C_EEPROM_DEV_ADDR,
1167 eeprom_data);
1168 }
1169
1170 /**
1171 * txgbe_read_i2c_sff8472 - Reads 8 bit word over I2C interface
1172 * @hw: pointer to hardware structure
1173 * @byte_offset: byte offset at address 0xA2
1174 * @sff8472_data: value read
1175 *
1176 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1177 **/
txgbe_read_i2c_sff8472(struct txgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1178 s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset,
1179 u8 *sff8472_data)
1180 {
1181 return hw->phy.read_i2c_byte(hw, byte_offset,
1182 TXGBE_I2C_EEPROM_DEV_ADDR2,
1183 sff8472_data);
1184 }
1185
1186 /**
1187 * txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1188 * @hw: pointer to hardware structure
1189 * @byte_offset: EEPROM byte offset to write
1190 * @eeprom_data: value to write
1191 *
1192 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1193 **/
txgbe_write_i2c_eeprom(struct txgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1194 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1195 u8 eeprom_data)
1196 {
1197 return hw->phy.write_i2c_byte(hw, byte_offset,
1198 TXGBE_I2C_EEPROM_DEV_ADDR,
1199 eeprom_data);
1200 }
1201
1202 /**
1203 * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C
1204 * @hw: pointer to hardware structure
1205 * @byte_offset: byte offset to read
1206 * @dev_addr: address to read from
1207 * @data: value read
1208 *
1209 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1210 * a specified device address.
1211 **/
txgbe_read_i2c_byte_unlocked(struct txgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)1212 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1213 u8 dev_addr, u8 *data)
1214 {
1215 txgbe_i2c_start(hw, dev_addr);
1216
1217 /* wait tx empty */
1218 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1219 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1220 return -TERR_TIMEOUT;
1221 }
1222
1223 /* read data */
1224 wr32(hw, TXGBE_I2CDATA,
1225 byte_offset | TXGBE_I2CDATA_STOP);
1226 wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ);
1227
1228 /* wait for read complete */
1229 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1230 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1231 return -TERR_TIMEOUT;
1232 }
1233
1234 txgbe_i2c_stop(hw);
1235
1236 *data = 0xFF & rd32(hw, TXGBE_I2CDATA);
1237
1238 return 0;
1239 }
1240
1241 /**
1242 * txgbe_read_i2c_byte - Reads 8 bit word over I2C
1243 * @hw: pointer to hardware structure
1244 * @byte_offset: byte offset to read
1245 * @dev_addr: address to read from
1246 * @data: value read
1247 *
1248 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1249 * a specified device address.
1250 **/
txgbe_read_i2c_byte(struct txgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)1251 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1252 u8 dev_addr, u8 *data)
1253 {
1254 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1255 int err = 0;
1256
1257 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1258 return TXGBE_ERR_SWFW_SYNC;
1259 err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1260 hw->mac.release_swfw_sync(hw, swfw_mask);
1261 return err;
1262 }
1263
1264 /**
1265 * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1266 * @hw: pointer to hardware structure
1267 * @byte_offset: byte offset to write
1268 * @dev_addr: address to write to
1269 * @data: value to write
1270 *
1271 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1272 * a specified device address.
1273 **/
txgbe_write_i2c_byte_unlocked(struct txgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)1274 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1275 u8 dev_addr, u8 data)
1276 {
1277 txgbe_i2c_start(hw, dev_addr);
1278
1279 /* wait tx empty */
1280 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1281 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1282 return -TERR_TIMEOUT;
1283 }
1284
1285 wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP);
1286 wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE);
1287
1288 /* wait for write complete */
1289 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1290 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1291 return -TERR_TIMEOUT;
1292 }
1293 txgbe_i2c_stop(hw);
1294
1295 return 0;
1296 }
1297
1298 /**
1299 * txgbe_write_i2c_byte - Writes 8 bit word over I2C
1300 * @hw: pointer to hardware structure
1301 * @byte_offset: byte offset to write
1302 * @dev_addr: address to write to
1303 * @data: value to write
1304 *
1305 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1306 * a specified device address.
1307 **/
txgbe_write_i2c_byte(struct txgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)1308 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1309 u8 dev_addr, u8 data)
1310 {
1311 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1312 int err = 0;
1313
1314 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1315 return TXGBE_ERR_SWFW_SYNC;
1316 err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1317 hw->mac.release_swfw_sync(hw, swfw_mask);
1318
1319 return err;
1320 }
1321
1322 /**
1323 * txgbe_i2c_start - Sets I2C start condition
1324 * @hw: pointer to hardware structure
1325 *
1326 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1327 **/
txgbe_i2c_start(struct txgbe_hw * hw,u8 dev_addr)1328 static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr)
1329 {
1330 wr32(hw, TXGBE_I2CENA, 0);
1331
1332 wr32(hw, TXGBE_I2CCON,
1333 (TXGBE_I2CCON_MENA |
1334 TXGBE_I2CCON_SPEED(1) |
1335 TXGBE_I2CCON_RESTART |
1336 TXGBE_I2CCON_SDIA));
1337 wr32(hw, TXGBE_I2CTAR, dev_addr >> 1);
1338 wr32(hw, TXGBE_I2CSSSCLHCNT, 200);
1339 wr32(hw, TXGBE_I2CSSSCLLCNT, 200);
1340 wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */
1341 wr32(hw, TXGBE_I2CTXTL, 4);
1342 wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF);
1343 wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF);
1344
1345 wr32(hw, TXGBE_I2CICM, 0);
1346 wr32(hw, TXGBE_I2CENA, 1);
1347 }
1348
1349 /**
1350 * txgbe_i2c_stop - Sets I2C stop condition
1351 * @hw: pointer to hardware structure
1352 *
1353 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1354 **/
txgbe_i2c_stop(struct txgbe_hw * hw)1355 static void txgbe_i2c_stop(struct txgbe_hw *hw)
1356 {
1357 /* wait for completion */
1358 if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST,
1359 0, NULL, 100, 100)) {
1360 DEBUGOUT("i2c stop timeout.");
1361 }
1362
1363 wr32(hw, TXGBE_I2CENA, 0);
1364 }
1365
1366 static void
txgbe_set_sgmii_an37_ability(struct txgbe_hw * hw)1367 txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)
1368 {
1369 u32 value;
1370
1371 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002);
1372 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105);
1373 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200);
1374 value = rd32_epcs(hw, SR_MII_MMD_CTL);
1375 value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9);
1376 wr32_epcs(hw, SR_MII_MMD_CTL, value);
1377 }
1378
1379 static s32
txgbe_set_link_to_kr(struct txgbe_hw * hw,bool autoneg)1380 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
1381 {
1382 u32 i;
1383 u16 value;
1384 s32 err = 0;
1385
1386 /* 1. Wait xpcs power-up good */
1387 for (i = 0; i < 100; i++) {
1388 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1389 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1390 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1391 break;
1392 msec_delay(10);
1393 }
1394 if (i == 100) {
1395 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1396 goto out;
1397 }
1398 BP_LOG("It is set to kr.\n");
1399
1400 wr32_epcs(hw, VR_AN_INTR_MSK, 0x7);
1401 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);
1402 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);
1403
1404 if (!autoneg) {
1405 /* 2. Disable xpcs AN-73 */
1406 wr32_epcs(hw, SR_AN_CTRL,
1407 SR_AN_CTRL_AN_EN | SR_AN_CTRL_EXT_NP);
1408
1409 wr32_epcs(hw, VR_AN_KR_MODE_CL, VR_AN_KR_MODE_CL_PDET);
1410
1411 if (!(hw->devarg.auto_neg == 1)) {
1412 wr32_epcs(hw, SR_AN_CTRL, 0);
1413 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
1414 } else {
1415 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
1416 value &= ~(1 << 6);
1417 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1418 }
1419 if (hw->devarg.present == 1) {
1420 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
1421 value |= TXGBE_PHY_TX_EQ_CTL1_DEF;
1422 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1423 }
1424 if (hw->devarg.poll == 1) {
1425 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL0,
1426 VR_PMA_KRTR_TIMER_MAX_WAIT);
1427 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL2, 0xA697);
1428 }
1429
1430 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1431 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16)
1432 */
1433 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1434 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR);
1435
1436 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1437 * Bit[12:8](RX_VREF_CTRL) = 5'hF (default: 5'h11)
1438 */
1439 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1440
1441 /* 5. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1442 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
1443 * Bit[7:5](CTLE_POLE_0) = 3'h2
1444 * Bit[4:0](CTLE_BOOST_0) = 4'hA
1445 */
1446 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774A);
1447
1448 /* 6. Set VR_MII_Gen5_12G_RX_GENCTRL3 Register
1449 * Bit[2:0](LOS_TRSHLD_0) = 3'h4 (default: 3)
1450 */
1451 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, 0x0004);
1452
1453 /* 7. Initialize the mode by setting VR XS or PCS MMD Digital
1454 * Control1 Register Bit[15](VR_RST)
1455 */
1456 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1457
1458 /* Wait phy initialization done */
1459 for (i = 0; i < 100; i++) {
1460 if ((rd32_epcs(hw,
1461 VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1462 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1463 break;
1464 msleep(100);
1465 }
1466 if (i == 100) {
1467 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1468 goto out;
1469 }
1470 } else {
1471 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);
1472 }
1473
1474 if (hw->phy.ffe_set == TXGBE_BP_M_KR) {
1475 value = (0x1804 & ~0x3F3F);
1476 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
1477 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1478
1479 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
1480 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1481 }
1482 out:
1483 return err;
1484 }
1485
1486 static s32
txgbe_set_link_to_kx4(struct txgbe_hw * hw,bool autoneg)1487 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
1488 {
1489 u32 i;
1490 s32 err = 0;
1491 u32 value;
1492
1493 /* Check link status, if already set, skip setting it again */
1494 if (hw->link_status == TXGBE_LINK_STATUS_KX4)
1495 goto out;
1496
1497 BP_LOG("It is set to kx4.\n");
1498 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0);
1499 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0);
1500
1501 /* 1. Wait xpcs power-up good */
1502 for (i = 0; i < 100; i++) {
1503 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1504 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1505 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1506 break;
1507 msec_delay(10);
1508 }
1509 if (i == 100) {
1510 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1511 goto out;
1512 }
1513
1514 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1515 ~TXGBE_MACTXCFG_TXE);
1516
1517 /* 2. Disable xpcs AN-73 */
1518 if (!autoneg)
1519 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1520 else
1521 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1522
1523 /* Disable PHY MPLLA for eth mode change(after ECO) */
1524 wr32_ephy(hw, 0x4, 0x250A);
1525 txgbe_flush(hw);
1526 msec_delay(1);
1527
1528 /* Set the eth change_mode bit first in mis_rst register
1529 * for corresponding LAN port
1530 */
1531 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1532
1533 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1534 * PCS_TYPE_SEL: non KR
1535 */
1536 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1537 SR_PCS_CTRL2_TYPE_SEL_X);
1538
1539 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b1
1540 * SS13: 10G speed
1541 */
1542 wr32_epcs(hw, SR_PMA_CTRL1,
1543 SR_PMA_CTRL1_SS13_KX4);
1544
1545 value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0xF0;
1546 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1547
1548 if ((hw->subsystem_device_id & 0xFF) == TXGBE_DEV_ID_MAC_XAUI)
1549 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1550 else
1551 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1552
1553 for (i = 0; i < 4; i++) {
1554 if (i == 0)
1555 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1556 (0x7 << 8) | 0x6;
1557 else
1558 value = (0xff06 & ~0xFFFF) | (0x7 << 12) |
1559 (0x7 << 8) | 0x6;
1560 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1561 }
1562
1563 value = 0x0 & ~0x7777;
1564 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1565
1566 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1567
1568 value = (0x6db & ~0xFFF) | (0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1;
1569 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1570
1571 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA
1572 * Control 0 Register Bit[7:0] = 8'd40 //MPLLA_MULTIPLIER
1573 */
1574 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1575 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER);
1576
1577 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA
1578 * Control 3 Register Bit[10:0] = 11'd86 //MPLLA_BANDWIDTH
1579 */
1580 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1581 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER);
1582
1583 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1584 * Calibration Load 0 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_0
1585 */
1586 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1587 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1588
1589 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1590 * Calibration Load 1 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_1
1591 */
1592 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1,
1593 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1594
1595 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1596 * Calibration Load 2 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_2
1597 */
1598 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2,
1599 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1600 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1601 * Calibration Load 3 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_3
1602 */
1603 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3,
1604 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1605 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1606 * Calibration Reference 0 Register Bit[5:0] = 6'd34 //VCO_REF_LD_0/1
1607 */
1608 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x2222);
1609
1610 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1611 * Calibration Reference 1 Register Bit[5:0] = 6'd34 //VCO_REF_LD_2/3
1612 */
1613 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2222);
1614
1615 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1616 * Enable Register Bit[7:0] = 8'd0 //AFE_EN_0/3_1, DFE_EN_0/3_1
1617 */
1618 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
1619
1620 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1621 * Equalization Control 4 Register Bit[3:0] = 4'd0 //CONT_ADAPT_0/3_1
1622 */
1623 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x00F0);
1624
1625 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1626 * Control Register Bit[14:12], Bit[10:8], Bit[6:4], Bit[2:0],
1627 * all rates to 3'b010 //TX0/1/2/3_RATE
1628 */
1629 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x2222);
1630
1631 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1632 * Control Register Bit[13:12], Bit[9:8], Bit[5:4], Bit[1:0],
1633 * all rates to 2'b10 //RX0/1/2/3_RATE
1634 */
1635 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x2222);
1636
1637 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1638 * Control 2 Register Bit[15:8] = 2'b01 //TX0/1/2/3_WIDTH: 10bits
1639 */
1640 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x5500);
1641
1642 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1643 * Control 2 Register Bit[15:8] = 2'b01 //RX0/1/2/3_WIDTH: 10bits
1644 */
1645 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x5500);
1646
1647 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1648 * 2 Register Bit[10:8] = 3'b010
1649 * MPLLA_DIV16P5_CLK_EN=0, MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1650 */
1651 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1652 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1653
1654 wr32_epcs(hw, 0x1f0000, 0x0);
1655 wr32_epcs(hw, 0x1f8001, 0x0);
1656 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0);
1657
1658 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1659 * Register Bit[15](VR_RST)
1660 */
1661 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1662
1663 /* Wait phy initialization done */
1664 for (i = 0; i < 100; i++) {
1665 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1666 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1667 break;
1668 msleep(100);
1669 }
1670
1671 /* If success, set link status */
1672 hw->link_status = TXGBE_LINK_STATUS_KX4;
1673
1674 if (i == 100) {
1675 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1676 goto out;
1677 }
1678
1679 if (hw->phy.ffe_set == TXGBE_BP_M_KX4) {
1680 value = (0x1804 & ~0x3F3F);
1681 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
1682 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1683
1684 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
1685 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1686 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
1687 value = (0x1804 & ~0x3F3F);
1688 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1689
1690 value = (0x50 & ~0x7F) | 40 | (1 << 6);
1691 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1692 }
1693 out:
1694 return err;
1695 }
1696
1697 static s32
txgbe_set_link_to_kx(struct txgbe_hw * hw,u32 speed,bool autoneg)1698 txgbe_set_link_to_kx(struct txgbe_hw *hw,
1699 u32 speed,
1700 bool autoneg)
1701 {
1702 u32 i;
1703 s32 err = 0;
1704 u32 wdata = 0;
1705 u32 value;
1706
1707 /* Check link status, if already set, skip setting it again */
1708 if (hw->link_status == TXGBE_LINK_STATUS_KX)
1709 goto out;
1710
1711 BP_LOG("It is set to kx. speed =0x%x\n", speed);
1712 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);
1713 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);
1714
1715 /* 1. Wait xpcs power-up good */
1716 for (i = 0; i < 100; i++) {
1717 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1718 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1719 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1720 break;
1721 msec_delay(10);
1722 }
1723 if (i == 100) {
1724 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1725 goto out;
1726 }
1727
1728 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1729 ~TXGBE_MACTXCFG_TXE);
1730
1731 /* 2. Disable xpcs AN-73 */
1732 if (!autoneg)
1733 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1734 else
1735 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1736
1737 /* Disable PHY MPLLA for eth mode change(after ECO) */
1738 wr32_ephy(hw, 0x4, 0x240A);
1739 txgbe_flush(hw);
1740 msec_delay(1);
1741
1742 /* Set the eth change_mode bit first in mis_rst register
1743 * for corresponding LAN port
1744 */
1745 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1746
1747 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1748 * PCS_TYPE_SEL: non KR
1749 */
1750 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1751 SR_PCS_CTRL2_TYPE_SEL_X);
1752
1753 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
1754 * SS13: 1G speed
1755 */
1756 wr32_epcs(hw, SR_PMA_CTRL1,
1757 SR_PMA_CTRL1_SS13_KX);
1758
1759 /* Set SR MII MMD Control Register to corresponding speed: {Bit[6],
1760 * Bit[13]}=[2'b00,2'b01,2'b10]->[10M,100M,1G]
1761 */
1762 if (speed == TXGBE_LINK_SPEED_100M_FULL)
1763 wdata = 0x2100;
1764 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1765 wdata = 0x0140;
1766 else if (speed == TXGBE_LINK_SPEED_10M_FULL)
1767 wdata = 0x0100;
1768 wr32_epcs(hw, SR_MII_MMD_CTL,
1769 wdata);
1770
1771 value = (0xf5f0 & ~0x710) | (0x5 << 8) | 0x10;
1772 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1773
1774 if (hw->devarg.sgmii == 1)
1775 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1776 else
1777 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1778
1779 for (i = 0; i < 4; i++) {
1780 if (i) {
1781 value = 0xff06;
1782 } else {
1783 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1784 (0x7 << 8) | 0x6;
1785 }
1786 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1787 }
1788
1789 value = 0x0 & ~0x7;
1790 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1791
1792 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1793
1794 value = (0x6db & ~0x7) | 0x4;
1795 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1796
1797 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1798 * 0 Register Bit[7:0] = 8'd32 //MPLLA_MULTIPLIER
1799 */
1800 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1801 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX);
1802
1803 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA Control
1804 * 3 Register Bit[10:0] = 11'd70 //MPLLA_BANDWIDTH
1805 */
1806 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1807 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX);
1808
1809 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1810 * Calibration Load 0 Register Bit[12:0] = 13'd1344 //VCO_LD_VAL_0
1811 */
1812 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1813 TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX);
1814
1815 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 0x549);
1816 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 0x549);
1817 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 0x549);
1818
1819 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1820 * Calibration Reference 0 Register Bit[5:0] = 6'd42 //VCO_REF_LD_0
1821 */
1822 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0,
1823 TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX);
1824
1825 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2929);
1826
1827 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1828 * Enable Register Bit[4], Bit[0] = 1'b0 //AFE_EN_0, DFE_EN_0
1829 */
1830 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE,
1831 0x0);
1832 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1833 * Equalization Control 4 Register Bit[0] = 1'b0 //CONT_ADAPT_0
1834 */
1835 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL,
1836 0x0010);
1837 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1838 * Control Register Bit[2:0] = 3'b011 //TX0_RATE
1839 */
1840 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL,
1841 TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX);
1842
1843 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1844 * Control Register Bit[2:0] = 3'b011 //RX0_RATE
1845 */
1846 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL,
1847 TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX);
1848
1849 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1850 * Control 2 Register Bit[9:8] = 2'b01 //TX0_WIDTH: 10bits
1851 */
1852 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2,
1853 TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER);
1854 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1855 * Control 2 Register Bit[9:8] = 2'b01 //RX0_WIDTH: 10bits
1856 */
1857 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2,
1858 TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER);
1859 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1860 * 2 Register Bit[10:8] = 3'b010 //MPLLA_DIV16P5_CLK_EN=0,
1861 * MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1862 */
1863 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1864 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1865
1866 /* VR MII MMD AN Control Register Bit[8] = 1'b1 //MII_CTRL
1867 * Set to 8bit MII (required in 10M/100M SGMII)
1868 */
1869 wr32_epcs(hw, SR_MII_MMD_AN_CTL,
1870 0x0100);
1871
1872 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1873 * Register Bit[15](VR_RST)
1874 */
1875 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1876
1877 /* Wait phy initialization done */
1878 for (i = 0; i < 100; i++) {
1879 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1880 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1881 break;
1882 msleep(100);
1883 }
1884
1885 /* If success, set link status */
1886 hw->link_status = TXGBE_LINK_STATUS_KX;
1887
1888 if (i == 100) {
1889 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1890 goto out;
1891 }
1892
1893 if (hw->phy.ffe_set == TXGBE_BP_M_KX) {
1894 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;
1895 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
1896 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1897
1898 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;
1899 value |= hw->phy.ffe_post | (1 << 6);
1900 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1901 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
1902 value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
1903 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1904
1905 value = (0x50 & ~0x7F) | 16 | (1 << 6);
1906 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1907 }
1908 out:
1909 return err;
1910 }
1911
1912 static s32
txgbe_set_link_to_sfi(struct txgbe_hw * hw,u32 speed)1913 txgbe_set_link_to_sfi(struct txgbe_hw *hw,
1914 u32 speed)
1915 {
1916 u32 i;
1917 s32 err = 0;
1918 u32 value = 0;
1919
1920 /* Set the module link speed */
1921 hw->mac.set_rate_select_speed(hw, speed);
1922 /* 1. Wait xpcs power-up good */
1923 for (i = 0; i < 100; i++) {
1924 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1925 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1926 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1927 break;
1928 msec_delay(10);
1929 }
1930 if (i == 100) {
1931 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1932 goto out;
1933 }
1934
1935 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1936 ~TXGBE_MACTXCFG_TXE);
1937
1938 /* 2. Disable xpcs AN-73 */
1939 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1940
1941 /* Disable PHY MPLLA for eth mode change(after ECO) */
1942 wr32_ephy(hw, 0x4, 0x243A);
1943 txgbe_flush(hw);
1944 msec_delay(1);
1945 /* Set the eth change_mode bit first in mis_rst register
1946 * for corresponding LAN port
1947 */
1948 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1949
1950 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
1951 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
1952 * PCS_TYPE_SEL: KR
1953 */
1954 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0);
1955 value = rd32_epcs(hw, SR_PMA_CTRL1);
1956 value = value | 0x2000;
1957 wr32_epcs(hw, SR_PMA_CTRL1, value);
1958 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL0 Register Bit[7:0] = 8'd33
1959 * MPLLA_MULTIPLIER
1960 */
1961 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0021);
1962 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1963 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd0
1964 */
1965 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0);
1966 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
1967 value = (value & ~0x700) | 0x500;
1968 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1969 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1970 * Bit[12:8](RX_VREF_CTRL) = 5'hF
1971 */
1972 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1973 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_LD0 Register
1974 * Bit[12:0] = 13'd1353 //VCO_LD_VAL_0
1975 */
1976 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0549);
1977 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_REF0 Register
1978 * Bit[5:0] = 6'd41 //VCO_REF_LD_0
1979 */
1980 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x0029);
1981 /* Set VR_XS_PMA_Gen5_12G_TX_RATE_CTRL Register
1982 * Bit[2:0] = 3'b000 //TX0_RATE
1983 */
1984 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0);
1985 /* Set VR_XS_PMA_Gen5_12G_RX_RATE_CTRL Register
1986 * Bit[2:0] = 3'b000 //RX0_RATE
1987 */
1988 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0);
1989 /* Set VR_XS_PMA_Gen5_12G_TX_GENCTRL2 Register Bit[9:8] = 2'b11
1990 * TX0_WIDTH: 20bits
1991 */
1992 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0300);
1993 /* Set VR_XS_PMA_Gen5_12G_RX_GENCTRL2 Register Bit[9:8] = 2'b11
1994 * RX0_WIDTH: 20bits
1995 */
1996 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0300);
1997 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL2 Register
1998 * Bit[10:8] = 3'b110
1999 * MPLLA_DIV16P5_CLK_EN=1
2000 * MPLLA_DIV10_CLK_EN=1
2001 * MPLLA_DIV8_CLK_EN=0
2002 */
2003 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600);
2004
2005 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2006 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2007 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2008 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
2009 * Bit[7:5](CTLE_POLE_0) = 3'h2
2010 * Bit[4:0](CTLE_BOOST_0) = 4'hF
2011 */
2012 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
2013
2014 } else {
2015 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2016 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
2017 * Bit[7:5](CTLE_POLE_0) = 3'h2
2018 * Bit[4:0](CTLE_BOOST_0) = 4'hA
2019 */
2020 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
2021 value = (value & ~0xFFFF) | (2 << 5) | 0x05;
2022 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
2023 }
2024 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2025 value = (value & ~0x7) | 0x0;
2026 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2027
2028 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2029 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2030 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2031 * Bit[7:0](DFE_TAP1_0) = 8'd20
2032 */
2033 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0014);
2034 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2035 value = (value & ~0x11) | 0x11;
2036 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2037 } else {
2038 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2039 * Bit[7:0](DFE_TAP1_0) = 8'd20
2040 */
2041 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0xBE);
2042 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2043 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2044 */
2045 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2046 value = (value & ~0x11) | 0x0;
2047 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2048 }
2049 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL);
2050 value = value & ~0x1;
2051 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, value);
2052 } else {
2053 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
2054 * PCS_TYPE_SEL: KR
2055 */
2056 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0x1);
2057 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
2058 * SS13: 1G speed
2059 */
2060 wr32_epcs(hw, SR_PMA_CTRL1, 0x0000);
2061 /* Set SR MII MMD Control Register to corresponding speed */
2062 wr32_epcs(hw, SR_MII_MMD_CTL, 0x0140);
2063
2064 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
2065 value = (value & ~0x710) | 0x500;
2066 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
2067 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
2068 * Bit[12:8](RX_VREF_CTRL) = 5'hF
2069 */
2070 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
2071
2072 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2073 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2074 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
2075 } else {
2076 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2077 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
2078 * Bit[7:5](CTLE_POLE_0) = 3'h2
2079 * Bit[4:0](CTLE_BOOST_0) = 4'hA
2080 */
2081 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
2082 value = (value & ~0xFFFF) | 0x7706;
2083 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
2084 }
2085 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2086 value = (value & ~0x7) | 0x0;
2087 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2088 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2089 * Bit[7:0](DFE_TAP1_0) = 8'd00
2090 */
2091 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
2092 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2093 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2094 */
2095 value = rd32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3);
2096 value = (value & ~0x7) | 0x4;
2097 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
2098 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0020);
2099 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0x0046);
2100 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0540);
2101 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x002A);
2102 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
2103 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x0010);
2104 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x0003);
2105 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x0003);
2106 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0100);
2107 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0100);
2108 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0200);
2109 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0100);
2110 }
2111 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
2112 * Register Bit[15](VR_RST)
2113 */
2114 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
2115
2116 /* Wait phy initialization done */
2117 for (i = 0; i < 100; i++) {
2118 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
2119 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
2120 break;
2121 msleep(100);
2122 }
2123 if (i == 100) {
2124 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
2125 goto out;
2126 }
2127
2128 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) {
2129 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;
2130 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
2131 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2132
2133 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;
2134 value |= hw->phy.ffe_post | (1 << 6);
2135 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2136 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
2137 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2138 value = (value & ~0x3F3F) | (24 << 8) | 4;
2139 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2140
2141 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2142 value = (value & ~0x7F) | 16 | (1 << 6);
2143 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2144 }
2145 out:
2146 return err;
2147 }
2148
2149 /**
2150 * txgbe_autoc_read - Hides MAC differences needed for AUTOC read
2151 * @hw: pointer to hardware structure
2152 */
txgbe_autoc_read(struct txgbe_hw * hw)2153 u64 txgbe_autoc_read(struct txgbe_hw *hw)
2154 {
2155 u64 autoc;
2156 u32 sr_pcs_ctl;
2157 u32 sr_pma_ctl1;
2158 u32 sr_an_ctl;
2159 u32 sr_an_adv_reg2;
2160 u8 type = hw->subsystem_device_id & 0xFF;
2161
2162 autoc = hw->mac.autoc;
2163
2164 if (hw->phy.multispeed_fiber) {
2165 autoc |= TXGBE_AUTOC_LMS_10G;
2166 } else if (type == TXGBE_DEV_ID_SFP) {
2167 autoc |= TXGBE_AUTOC_LMS_10G;
2168 autoc |= TXGBE_AUTOC_10GS_SFI;
2169 } else if (type == TXGBE_DEV_ID_QSFP) {
2170 autoc = 0; /*TBD*/
2171 } else if (type == TXGBE_DEV_ID_XAUI || type == TXGBE_DEV_ID_SFI_XAUI) {
2172 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2173 autoc |= TXGBE_AUTOC_10G_XAUI;
2174 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T;
2175 } else if (type == TXGBE_DEV_ID_SGMII) {
2176 autoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M;
2177 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T |
2178 TXGBE_PHYSICAL_LAYER_100BASE_TX;
2179 } else if (type == TXGBE_DEV_ID_MAC_XAUI) {
2180 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2181 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2182 } else if (type == TXGBE_DEV_ID_MAC_SGMII) {
2183 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
2184 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2185 }
2186
2187 if (type != TXGBE_DEV_ID_KR_KX_KX4)
2188 return autoc;
2189
2190 sr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2191 sr_pma_ctl1 = rd32_epcs(hw, SR_PMA_CTRL1);
2192 sr_an_ctl = rd32_epcs(hw, SR_AN_CTRL);
2193 sr_an_adv_reg2 = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
2194
2195 if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == SR_PCS_CTRL2_TYPE_SEL_X &&
2196 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX &&
2197 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2198 /* 1G or KX - no backplane auto-negotiation */
2199 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN |
2200 TXGBE_AUTOC_1G_KX;
2201 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2202 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2203 SR_PCS_CTRL2_TYPE_SEL_X &&
2204 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX4 &&
2205 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2206 autoc |= TXGBE_AUTOC_LMS_10G |
2207 TXGBE_AUTOC_10G_KX4;
2208 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2209 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2210 SR_PCS_CTRL2_TYPE_SEL_R &&
2211 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2212 /* 10 GbE serial link (KR -no backplane auto-negotiation) */
2213 autoc |= TXGBE_AUTOC_LMS_10G |
2214 TXGBE_AUTOC_10GS_KR;
2215 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR;
2216 } else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) {
2217 /* KX/KX4/KR backplane auto-negotiation enable */
2218 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR)
2219 autoc |= TXGBE_AUTOC_KR_SUPP;
2220 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4)
2221 autoc |= TXGBE_AUTOC_KX4_SUPP;
2222 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX)
2223 autoc |= TXGBE_AUTOC_KX_SUPP;
2224 autoc |= TXGBE_AUTOC_LMS_KX4_KX_KR;
2225 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR |
2226 TXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2227 TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2228 }
2229
2230 return autoc;
2231 }
2232
2233 /**
2234 * txgbe_autoc_write - Hides MAC differences needed for AUTOC write
2235 * @hw: pointer to hardware structure
2236 * @autoc: value to write to AUTOC
2237 */
txgbe_autoc_write(struct txgbe_hw * hw,u64 autoc)2238 void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
2239 {
2240 bool autoneg;
2241 u32 speed;
2242 u32 mactxcfg = 0;
2243 u8 device_type = hw->subsystem_device_id & 0xFF;
2244
2245 speed = TXGBD_AUTOC_SPEED(autoc);
2246 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2247 autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);
2248 autoc &= ~TXGBE_AUTOC_AUTONEG;
2249
2250 if (device_type == TXGBE_DEV_ID_KR_KX_KX4) {
2251 if (!autoneg) {
2252 switch (hw->phy.link_mode) {
2253 case TXGBE_PHYSICAL_LAYER_10GBASE_KR:
2254 txgbe_set_link_to_kr(hw, autoneg);
2255 break;
2256 case TXGBE_PHYSICAL_LAYER_10GBASE_KX4:
2257 txgbe_set_link_to_kx4(hw, autoneg);
2258 break;
2259 case TXGBE_PHYSICAL_LAYER_1000BASE_KX:
2260 txgbe_set_link_to_kx(hw, speed, autoneg);
2261 break;
2262 default:
2263 return;
2264 }
2265 } else {
2266 txgbe_set_link_to_kr(hw, !autoneg);
2267 }
2268 } else if (device_type == TXGBE_DEV_ID_XAUI ||
2269 device_type == TXGBE_DEV_ID_SGMII ||
2270 device_type == TXGBE_DEV_ID_MAC_XAUI ||
2271 device_type == TXGBE_DEV_ID_MAC_SGMII ||
2272 (device_type == TXGBE_DEV_ID_SFI_XAUI &&
2273 hw->phy.media_type == txgbe_media_type_copper)) {
2274 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
2275 txgbe_set_link_to_kx4(hw, 0);
2276 } else {
2277 txgbe_set_link_to_kx(hw, speed, 0);
2278 if (hw->devarg.auto_neg == 1)
2279 txgbe_set_sgmii_an37_ability(hw);
2280 }
2281 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2282 txgbe_set_link_to_sfi(hw, speed);
2283 }
2284
2285 if (speed == TXGBE_LINK_SPEED_10GB_FULL)
2286 mactxcfg = TXGBE_MACTXCFG_SPEED_10G;
2287 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
2288 mactxcfg = TXGBE_MACTXCFG_SPEED_1G;
2289
2290 /* enable mac transmitter */
2291 wr32m(hw, TXGBE_MACTXCFG,
2292 TXGBE_MACTXCFG_SPEED_MASK | TXGBE_MACTXCFG_TXE,
2293 mactxcfg | TXGBE_MACTXCFG_TXE);
2294 }
2295
txgbe_bp_down_event(struct txgbe_hw * hw)2296 void txgbe_bp_down_event(struct txgbe_hw *hw)
2297 {
2298 if (!(hw->devarg.auto_neg == 1))
2299 return;
2300
2301 BP_LOG("restart phy power.\n");
2302 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
2303 wr32_epcs(hw, SR_AN_CTRL, 0);
2304 wr32_epcs(hw, VR_AN_INTR_MSK, 0);
2305
2306 msleep(1050);
2307 txgbe_set_link_to_kr(hw, 0);
2308 }
2309
txgbe_bp_mode_set(struct txgbe_hw * hw)2310 void txgbe_bp_mode_set(struct txgbe_hw *hw)
2311 {
2312 if (hw->phy.ffe_set == TXGBE_BP_M_SFI)
2313 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_SFP;
2314 else if (hw->phy.ffe_set == TXGBE_BP_M_KR)
2315 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_KR_KX_KX4;
2316 else if (hw->phy.ffe_set == TXGBE_BP_M_KX4)
2317 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_XAUI;
2318 else if (hw->phy.ffe_set == TXGBE_BP_M_KX)
2319 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_SGMII;
2320 }
2321
txgbe_set_phy_temp(struct txgbe_hw * hw)2322 void txgbe_set_phy_temp(struct txgbe_hw *hw)
2323 {
2324 u32 value;
2325
2326 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) {
2327 BP_LOG("Set SFI TX_EQ MAIN:%d PRE:%d POST:%d\n",
2328 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
2329
2330 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2331 value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |
2332 hw->phy.ffe_pre;
2333 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2334
2335 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2336 value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);
2337 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2338 }
2339
2340 if (hw->phy.ffe_set == TXGBE_BP_M_KR) {
2341 BP_LOG("Set KR TX_EQ MAIN:%d PRE:%d POST:%d\n",
2342 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
2343 value = (0x1804 & ~0x3F3F);
2344 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
2345 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2346
2347 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
2348 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2349 wr32_epcs(hw, 0x18035, 0x00FF);
2350 wr32_epcs(hw, 0x18055, 0x00FF);
2351 }
2352
2353 if (hw->phy.ffe_set == TXGBE_BP_M_KX) {
2354 BP_LOG("Set KX TX_EQ MAIN:%d PRE:%d POST:%d\n",
2355 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
2356 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2357 value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |
2358 hw->phy.ffe_pre;
2359 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2360
2361 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2362 value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);
2363 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2364
2365 wr32_epcs(hw, 0x18035, 0x00FF);
2366 wr32_epcs(hw, 0x18055, 0x00FF);
2367 }
2368 }
2369
2370 /**
2371 * txgbe_kr_handle - Handle the interrupt of auto-negotiation
2372 * @hw: pointer to hardware structure
2373 */
txgbe_kr_handle(struct txgbe_hw * hw)2374 s32 txgbe_kr_handle(struct txgbe_hw *hw)
2375 {
2376 u32 value;
2377 s32 status = 0;
2378
2379 value = rd32_epcs(hw, VR_AN_INTR);
2380 BP_LOG("AN INTERRUPT!! value: 0x%x\n", value);
2381 if (!(value & VR_AN_INTR_PG_RCV)) {
2382 wr32_epcs(hw, VR_AN_INTR, 0);
2383 return status;
2384 }
2385
2386 status = txgbe_handle_bp_flow(0, hw);
2387
2388 return status;
2389 }
2390
2391 /**
2392 * txgbe_handle_bp_flow - Handle backplane AN73 flow
2393 * @hw: pointer to hardware structure
2394 * @link_mode: local AN73 link mode
2395 */
txgbe_handle_bp_flow(u32 link_mode,struct txgbe_hw * hw)2396 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw)
2397 {
2398 u32 value, i, lp_reg, ld_reg;
2399 s32 status = 0;
2400 struct txgbe_backplane_ability local_ability, lp_ability;
2401
2402 local_ability.current_link_mode = link_mode;
2403
2404 /* 1. Get the local AN73 Base Page Ability */
2405 BP_LOG("<1>. Get the local AN73 Base Page Ability ...\n");
2406 txgbe_get_bp_ability(&local_ability, 0, hw);
2407
2408 /* 2. Check and clear the AN73 Interrupt Status */
2409 BP_LOG("<2>. Check the AN73 Interrupt Status ...\n");
2410 txgbe_clear_bp_intr(2, 0, hw);
2411
2412 /* 3.1. Get the link partner AN73 Base Page Ability */
2413 BP_LOG("<3.1>. Get the link partner AN73 Base Page Ability ...\n");
2414 txgbe_get_bp_ability(&lp_ability, 1, hw);
2415
2416 /* 3.2. Check the AN73 Link Ability with Link Partner */
2417 BP_LOG("<3.2>. Check the AN73 Link Ability with Link Partner ...\n");
2418 BP_LOG(" Local Link Ability: 0x%x\n", local_ability.link_ability);
2419 BP_LOG(" Link Partner Link Ability: 0x%x\n", lp_ability.link_ability);
2420
2421 status = txgbe_check_bp_ability(&local_ability, &lp_ability, hw);
2422
2423 wr32_epcs(hw, SR_AN_CTRL, 0);
2424 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
2425
2426 /* 3.3. Check the FEC and KR Training for KR mode */
2427 BP_LOG("<3.3>. Check the FEC for KR mode ...\n");
2428 if ((local_ability.fec_ability & lp_ability.fec_ability) == 0x03) {
2429 BP_LOG("Enable the Backplane KR FEC ...\n");
2430 wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, SR_PMA_KR_FEC_CTRL_EN);
2431 } else {
2432 BP_LOG("Backplane KR FEC is disabled.\n");
2433 }
2434
2435 printf("Enter training.\n");
2436 /* CL72 KR training on */
2437 for (i = 0; i < 2; i++) {
2438 /* 3.4. Check the CL72 KR Training for KR mode */
2439 BP_LOG("<3.4>. Check the CL72 KR Training for KR mode ...\n");
2440 BP_LOG("==================%d==================\n", i);
2441 status = txgbe_enable_kr_training(hw);
2442 BP_LOG("Check the Clause 72 KR Training status ...\n");
2443 status |= txgbe_check_kr_training(hw);
2444
2445 lp_reg = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2446 lp_reg &= SR_PMA_KR_LP_CESTS_RR;
2447 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n",
2448 lp_reg);
2449 ld_reg = rd32_epcs(hw, SR_PMA_KR_LD_CESTS);
2450 ld_reg &= SR_PMA_KR_LD_CESTS_RR;
2451 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status Register: 0x%x\n",
2452 ld_reg);
2453 if (hw->devarg.poll == 0 && status != 0)
2454 lp_reg = SR_PMA_KR_LP_CESTS_RR;
2455
2456 if (lp_reg & ld_reg) {
2457 BP_LOG("==================out==================\n");
2458 status = txgbe_disable_kr_training(hw, 0, 0);
2459 wr32_epcs(hw, SR_AN_CTRL, 0);
2460 txgbe_clear_bp_intr(2, 0, hw);
2461 txgbe_clear_bp_intr(1, 0, hw);
2462 txgbe_clear_bp_intr(0, 0, hw);
2463 for (i = 0; i < 10; i++) {
2464 value = rd32_epcs(hw, SR_XS_PCS_KR_STS1);
2465 if (value & SR_XS_PCS_KR_STS1_PLU) {
2466 BP_LOG("\nINT_AN_INT_CMPLT =1, AN73 Done Success.\n");
2467 wr32_epcs(hw, SR_AN_CTRL, 0);
2468 return 0;
2469 }
2470 msec_delay(10);
2471 }
2472 msec_delay(1000);
2473 txgbe_set_link_to_kr(hw, 0);
2474
2475 return 0;
2476 }
2477
2478 status |= txgbe_disable_kr_training(hw, 0, 0);
2479 }
2480
2481 txgbe_clear_bp_intr(2, 0, hw);
2482 txgbe_clear_bp_intr(1, 0, hw);
2483 txgbe_clear_bp_intr(0, 0, hw);
2484
2485 return status;
2486 }
2487
2488 /**
2489 * txgbe_get_bp_ability
2490 * @hw: pointer to hardware structure
2491 * @ability: pointer to blackplane ability structure
2492 * @link_partner:
2493 * 1: Get Link Partner Base Page
2494 * 2: Get Link Partner Next Page
2495 * (only get NXP Ability Register 1 at the moment)
2496 * 0: Get Local Device Base Page
2497 */
txgbe_get_bp_ability(struct txgbe_backplane_ability * ability,u32 link_partner,struct txgbe_hw * hw)2498 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
2499 u32 link_partner, struct txgbe_hw *hw)
2500 {
2501 u32 value = 0;
2502
2503 /* Link Partner Base Page */
2504 if (link_partner == 1) {
2505 /* Read the link partner AN73 Base Page Ability Registers */
2506 BP_LOG("Read the link partner AN73 Base Page Ability Registers...\n");
2507 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
2508 BP_LOG("SR AN MMD LP Base Page Ability Register 1: 0x%x\n",
2509 value);
2510 ability->next_page = SR_MMD_LP_ABL1_ADV_NP(value);
2511 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2512
2513 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL2);
2514 BP_LOG("SR AN MMD LP Base Page Ability Register 2: 0x%x\n",
2515 value);
2516 ability->link_ability =
2517 value & SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX;
2518 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n",
2519 ability->link_ability);
2520 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n");
2521 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n");
2522
2523 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL3);
2524 BP_LOG("SR AN MMD LP Base Page Ability Register 3: 0x%x\n",
2525 value);
2526 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01));
2527 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01));
2528 ability->fec_ability = SR_AN_MMD_LP_ABL3_FCE(value);
2529 } else if (link_partner == 2) {
2530 /* Read the link partner AN73 Next Page Ability Registers */
2531 BP_LOG("\nRead the link partner AN73 Next Page Ability Registers...\n");
2532 value = rd32_epcs(hw, SR_AN_LP_XNP_ABL1);
2533 BP_LOG(" SR AN MMD LP XNP Ability Register 1: 0x%x\n", value);
2534 ability->next_page = SR_AN_LP_XNP_ABL1_NP(value);
2535 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2536 } else {
2537 /* Read the local AN73 Base Page Ability Registers */
2538 BP_LOG("Read the local AN73 Base Page Ability Registers...\n");
2539 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
2540 BP_LOG("SR AN MMD Advertisement Register 1: 0x%x\n", value);
2541 ability->next_page = SR_AN_MMD_ADV_REG1_NP(value);
2542 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2543
2544 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
2545 BP_LOG("SR AN MMD Advertisement Register 2: 0x%x\n", value);
2546 ability->link_ability =
2547 value & SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX;
2548 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n",
2549 ability->link_ability);
2550 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n");
2551 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n");
2552
2553 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG3);
2554 BP_LOG("SR AN MMD Advertisement Register 3: 0x%x\n", value);
2555 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01));
2556 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01));
2557 ability->fec_ability = SR_AN_MMD_ADV_REG3_FCE(value);
2558 }
2559
2560 BP_LOG("done.\n");
2561 }
2562
2563 /**
2564 * txgbe_check_bp_ability
2565 * @hw: pointer to hardware structure
2566 * @ability: pointer to blackplane ability structure
2567 */
txgbe_check_bp_ability(struct txgbe_backplane_ability * local_ability,struct txgbe_backplane_ability * lp_ability,struct txgbe_hw * hw)2568 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability,
2569 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw)
2570 {
2571 u32 com_link_abi;
2572 s32 ret = 0;
2573
2574 com_link_abi = local_ability->link_ability & lp_ability->link_ability;
2575 BP_LOG("com_link_abi = 0x%x, local_ability = 0x%x, lp_ability = 0x%x\n",
2576 com_link_abi, local_ability->link_ability,
2577 lp_ability->link_ability);
2578
2579 if (!com_link_abi) {
2580 BP_LOG("The Link Partner does not support any compatible speed mode.\n");
2581 ret = -1;
2582 } else if (com_link_abi & BP_TYPE_KR) {
2583 if (local_ability->current_link_mode) {
2584 BP_LOG("Link mode is not matched with Link Partner: [LINK_KR].\n");
2585 BP_LOG("Set the local link mode to [LINK_KR] ...\n");
2586 txgbe_set_link_to_kr(hw, 0);
2587 ret = 1;
2588 } else {
2589 BP_LOG("Link mode is matched with Link Partner: [LINK_KR].\n");
2590 ret = 0;
2591 }
2592 } else if (com_link_abi & BP_TYPE_KX4) {
2593 if (local_ability->current_link_mode == 0x10) {
2594 BP_LOG("Link mode is matched with Link Partner: [LINK_KX4].\n");
2595 ret = 0;
2596 } else {
2597 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX4].\n");
2598 BP_LOG("Set the local link mode to [LINK_KX4] ...\n");
2599 txgbe_set_link_to_kx4(hw, 1);
2600 ret = 1;
2601 }
2602 } else if (com_link_abi & BP_TYPE_KX) {
2603 if (local_ability->current_link_mode == 0x1) {
2604 BP_LOG("Link mode is matched with Link Partner: [LINK_KX].\n");
2605 ret = 0;
2606 } else {
2607 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX].\n");
2608 BP_LOG("Set the local link mode to [LINK_KX] ...\n");
2609 txgbe_set_link_to_kx(hw, 1, 1);
2610 ret = 1;
2611 }
2612 }
2613
2614 return ret;
2615 }
2616
2617 /**
2618 * txgbe_clear_bp_intr
2619 * @hw: pointer to hardware structure
2620 * @index: the bit will be cleared
2621 * @index_high:
2622 * index_high = 0: Only the index bit will be cleared
2623 * index_high != 0: the [index_high, index] range will be cleared
2624 */
txgbe_clear_bp_intr(u32 bit,u32 bit_high,struct txgbe_hw * hw)2625 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw)
2626 {
2627 u32 rdata = 0, wdata, i;
2628
2629 rdata = rd32_epcs(hw, VR_AN_INTR);
2630 BP_LOG("[Before clear]Read VR AN MMD Interrupt Register: 0x%x\n",
2631 rdata);
2632 BP_LOG("Interrupt: 0- AN_INT_CMPLT, 1- AN_INC_LINK, 2- AN_PG_RCV\n\n");
2633
2634 wdata = rdata;
2635 if (bit_high) {
2636 for (i = bit; i <= bit_high; i++)
2637 wdata &= ~(1 << i);
2638 } else {
2639 wdata &= ~(1 << bit);
2640 }
2641
2642 wr32_epcs(hw, VR_AN_INTR, wdata);
2643
2644 rdata = rd32_epcs(hw, VR_AN_INTR);
2645 BP_LOG("[After clear]Read VR AN MMD Interrupt Register: 0x%x\n", rdata);
2646 }
2647
txgbe_enable_kr_training(struct txgbe_hw * hw)2648 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw)
2649 {
2650 s32 status = 0;
2651 u32 value = 0;
2652
2653 BP_LOG("Enable Clause 72 KR Training ...\n");
2654
2655 if (CL72_KRTR_PRBS_MODE_EN != 0xFFFF) {
2656 /* Set PRBS Timer Duration Control to maximum 6.7ms in
2657 * VR_PMA_KRTR_PRBS_CTRL2 Register
2658 */
2659 value = CL72_KRTR_PRBS_MODE_EN;
2660 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL2, value);
2661 /* Set PRBS Timer Duration Control to maximum 6.7ms in
2662 * VR_PMA_KRTR_PRBS_CTRL1 Register
2663 */
2664 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL1,
2665 VR_PMA_KRTR_PRBS_TIME_LMT);
2666 /* Enable PRBS Mode to determine KR Training Status by setting
2667 * Bit 0 of VR_PMA_KRTR_PRBS_CTRL0 Register
2668 */
2669 value = VR_PMA_KRTR_PRBS_MODE_EN;
2670 }
2671 #ifdef CL72_KRTR_PRBS31_EN
2672 /* Enable PRBS Mode to determine KR Training Status by setting
2673 * Bit 1 of VR_PMA_KRTR_PRBS_CTRL0 Register
2674 */
2675 value = VR_PMA_KRTR_PRBS31_EN;
2676 #endif
2677 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL0, value);
2678 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */
2679 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2680
2681 /* Enable the Clause 72 start-up protocol
2682 * by setting Bit 1 of SR_PMA_KR_PMD_CTRL Register.
2683 * Restart the Clause 72 start-up protocol
2684 * by setting Bit 0 of SR_PMA_KR_PMD_CTRL Register.
2685 */
2686 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL,
2687 SR_PMA_KR_PMD_CTRL_EN_TR | SR_PMA_KR_PMD_CTRL_RS_TR);
2688
2689 return status;
2690 }
2691
txgbe_disable_kr_training(struct txgbe_hw * hw,s32 post,s32 mode)2692 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode)
2693 {
2694 s32 status = 0;
2695
2696 BP_LOG("Disable Clause 72 KR Training ...\n");
2697 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */
2698 txgbe_read_phy_lane_tx_eq(0, hw, post, mode);
2699
2700 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, SR_PMA_KR_PMD_CTRL_RS_TR);
2701
2702 return status;
2703 }
2704
txgbe_check_kr_training(struct txgbe_hw * hw)2705 static s32 txgbe_check_kr_training(struct txgbe_hw *hw)
2706 {
2707 s32 status = 0;
2708 u32 value, test;
2709 int i;
2710 int times = hw->devarg.poll ? 35 : 20;
2711
2712 for (i = 0; i < times; i++) {
2713 value = rd32_epcs(hw, SR_PMA_KR_LP_CEU);
2714 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Update Register: 0x%x\n",
2715 value);
2716 value = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2717 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n",
2718 value);
2719 value = rd32_epcs(hw, SR_PMA_KR_LD_CEU);
2720 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Update: 0x%x\n",
2721 value);
2722 value = rd32_epcs(hw, SR_PMA_KR_LD_CESTS);
2723 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status: 0x%x\n",
2724 value);
2725 value = rd32_epcs(hw, SR_PMA_KR_PMD_STS);
2726 BP_LOG("SR PMA MMD 10GBASE-KR Status Register: 0x%x\n", value);
2727 BP_LOG(" Training Failure (bit3): %d\n",
2728 ((value >> 3) & 0x01));
2729 BP_LOG(" Start-Up Protocol Status (bit2): %d\n",
2730 ((value >> 2) & 0x01));
2731 BP_LOG(" Frame Lock (bit1): %d\n",
2732 ((value >> 1) & 0x01));
2733 BP_LOG(" Receiver Status (bit0): %d\n",
2734 ((value >> 0) & 0x01));
2735
2736 test = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2737 if (test & SR_PMA_KR_LP_CESTS_RR) {
2738 BP_LOG("TEST Coefficient Status Register: 0x%x\n",
2739 test);
2740 status = 1;
2741 }
2742
2743 if (value & SR_PMA_KR_PMD_STS_TR_FAIL) {
2744 BP_LOG("Training is completed with failure.\n");
2745 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2746 return 0;
2747 }
2748
2749 if (value & SR_PMA_KR_PMD_STS_RCV) {
2750 BP_LOG("Receiver trained and ready to receive data.\n");
2751 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2752 return 0;
2753 }
2754
2755 msec_delay(20);
2756 }
2757
2758 BP_LOG("ERROR: Check Clause 72 KR Training Complete Timeout.\n");
2759 return status;
2760 }
2761
txgbe_read_phy_lane_tx_eq(u16 lane,struct txgbe_hw * hw,s32 post,s32 mode)2762 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw,
2763 s32 post, s32 mode)
2764 {
2765 u32 value = 0;
2766 u32 addr;
2767 u32 tx_main_cursor, tx_pre_cursor, tx_post_cursor, lmain;
2768
2769 addr = TXGBE_PHY_LANE0_TX_EQ_CTL1 | (lane << 8);
2770 value = rd32_ephy(hw, addr);
2771 BP_LOG("PHY LANE TX EQ Read Value: %x\n", lane);
2772 tx_main_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(value);
2773 BP_LOG("TX_MAIN_CURSOR: %x\n", tx_main_cursor);
2774 UNREFERENCED_PARAMETER(tx_main_cursor);
2775
2776 addr = TXGBE_PHY_LANE0_TX_EQ_CTL2 | (lane << 8);
2777 value = rd32_ephy(hw, addr);
2778 tx_pre_cursor = value & TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE;
2779 tx_post_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(value);
2780 BP_LOG("TX_PRE_CURSOR: %x\n", tx_pre_cursor);
2781 BP_LOG("TX_POST_CURSOR: %x\n", tx_post_cursor);
2782
2783 if (mode == 1) {
2784 lmain = 160 - tx_pre_cursor - tx_post_cursor;
2785 if (lmain < 88)
2786 lmain = 88;
2787
2788 if (post)
2789 tx_post_cursor = post;
2790
2791 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL1, tx_post_cursor);
2792 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL0,
2793 tx_pre_cursor | (lmain << 8));
2794 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2795 value &= ~TXGBE_PHY_TX_EQ_CTL1_DEF;
2796 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2797 }
2798 }
2799