1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 #include "ixgbe_api.h"
6 #include "ixgbe_common.h"
7 #include "ixgbe_phy.h"
8
9 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
10 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
11 STATIC void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
12 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
13 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
14 STATIC void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
15 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
16 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
17 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
18 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
19 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
20 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
21 u8 *sff8472_data);
22
23 /**
24 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
25 * @hw: pointer to the hardware structure
26 * @byte: byte to send
27 *
28 * Returns an error code on error.
29 */
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,u8 byte)30 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
31 {
32 s32 status;
33
34 status = ixgbe_clock_out_i2c_byte(hw, byte);
35 if (status)
36 return status;
37 return ixgbe_get_i2c_ack(hw);
38 }
39
40 /**
41 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
42 * @hw: pointer to the hardware structure
43 * @byte: pointer to a u8 to receive the byte
44 *
45 * Returns an error code on error.
46 */
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,u8 * byte)47 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
48 {
49 ixgbe_clock_in_i2c_byte(hw, byte);
50 /* ACK */
51 return ixgbe_clock_out_i2c_bit(hw, false);
52 }
53
54 /**
55 * ixgbe_ones_comp_byte_add - Perform one's complement addition
56 * @add1: addend 1
57 * @add2: addend 2
58 *
59 * Returns one's complement 8-bit sum.
60 */
ixgbe_ones_comp_byte_add(u8 add1,u8 add2)61 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
62 {
63 u16 sum = add1 + add2;
64
65 sum = (sum & 0xFF) + (sum >> 8);
66 return sum & 0xFF;
67 }
68
69 /**
70 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
71 * @hw: pointer to the hardware structure
72 * @addr: I2C bus address to read from
73 * @reg: I2C device register to read from
74 * @val: pointer to location to receive read value
75 * @lock: true if to take and release semaphore
76 *
77 * Returns an error code on error.
78 */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val,bool lock)79 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
80 u16 *val, bool lock)
81 {
82 u32 swfw_mask = hw->phy.phy_semaphore_mask;
83 int max_retry = 3;
84 int retry = 0;
85 u8 csum_byte;
86 u8 high_bits;
87 u8 low_bits;
88 u8 reg_high;
89 u8 csum;
90
91 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
92 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
93 csum = ~csum;
94 do {
95 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
96 return IXGBE_ERR_SWFW_SYNC;
97 ixgbe_i2c_start(hw);
98 /* Device Address and write indication */
99 if (ixgbe_out_i2c_byte_ack(hw, addr))
100 goto fail;
101 /* Write bits 14:8 */
102 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
103 goto fail;
104 /* Write bits 7:0 */
105 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
106 goto fail;
107 /* Write csum */
108 if (ixgbe_out_i2c_byte_ack(hw, csum))
109 goto fail;
110 /* Re-start condition */
111 ixgbe_i2c_start(hw);
112 /* Device Address and read indication */
113 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
114 goto fail;
115 /* Get upper bits */
116 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
117 goto fail;
118 /* Get low bits */
119 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
120 goto fail;
121 /* Get csum */
122 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
123 /* NACK */
124 if (ixgbe_clock_out_i2c_bit(hw, false))
125 goto fail;
126 ixgbe_i2c_stop(hw);
127 if (lock)
128 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
129 *val = (high_bits << 8) | low_bits;
130 return 0;
131
132 fail:
133 ixgbe_i2c_bus_clear(hw);
134 if (lock)
135 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
136 if (retry < max_retry)
137 DEBUGOUT("I2C byte read combined error - Retrying.\n");
138 else
139 DEBUGOUT("I2C byte read combined error.\n");
140 retry++;
141 } while (retry <= max_retry);
142
143 return IXGBE_ERR_I2C;
144 }
145
146 /**
147 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
148 * @hw: pointer to the hardware structure
149 * @addr: I2C bus address to write to
150 * @reg: I2C device register to write to
151 * @val: value to write
152 * @lock: true if to take and release semaphore
153 *
154 * Returns an error code on error.
155 */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val,bool lock)156 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
157 u16 val, bool lock)
158 {
159 u32 swfw_mask = hw->phy.phy_semaphore_mask;
160 int max_retry = 1;
161 int retry = 0;
162 u8 reg_high;
163 u8 csum;
164
165 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
166 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
167 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
168 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
169 csum = ~csum;
170 do {
171 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
172 return IXGBE_ERR_SWFW_SYNC;
173 ixgbe_i2c_start(hw);
174 /* Device Address and write indication */
175 if (ixgbe_out_i2c_byte_ack(hw, addr))
176 goto fail;
177 /* Write bits 14:8 */
178 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
179 goto fail;
180 /* Write bits 7:0 */
181 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
182 goto fail;
183 /* Write data 15:8 */
184 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
185 goto fail;
186 /* Write data 7:0 */
187 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
188 goto fail;
189 /* Write csum */
190 if (ixgbe_out_i2c_byte_ack(hw, csum))
191 goto fail;
192 ixgbe_i2c_stop(hw);
193 if (lock)
194 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
195 return 0;
196
197 fail:
198 ixgbe_i2c_bus_clear(hw);
199 if (lock)
200 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
201 if (retry < max_retry)
202 DEBUGOUT("I2C byte write combined error - Retrying.\n");
203 else
204 DEBUGOUT("I2C byte write combined error.\n");
205 retry++;
206 } while (retry <= max_retry);
207
208 return IXGBE_ERR_I2C;
209 }
210
211 /**
212 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
213 * @hw: pointer to the hardware structure
214 *
215 * Initialize the function pointers.
216 **/
ixgbe_init_phy_ops_generic(struct ixgbe_hw * hw)217 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
218 {
219 struct ixgbe_phy_info *phy = &hw->phy;
220
221 DEBUGFUNC("ixgbe_init_phy_ops_generic");
222
223 /* PHY */
224 phy->ops.identify = ixgbe_identify_phy_generic;
225 phy->ops.reset = ixgbe_reset_phy_generic;
226 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
227 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
228 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
229 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
230 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
231 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
232 phy->ops.check_link = NULL;
233 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
234 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
235 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
236 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
237 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
238 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
239 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
240 phy->ops.identify_sfp = ixgbe_identify_module_generic;
241 phy->sfp_type = ixgbe_sfp_type_unknown;
242 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
243 phy->ops.write_i2c_byte_unlocked =
244 ixgbe_write_i2c_byte_generic_unlocked;
245 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
246 return IXGBE_SUCCESS;
247 }
248
249 /**
250 * ixgbe_probe_phy - Probe a single address for a PHY
251 * @hw: pointer to hardware structure
252 * @phy_addr: PHY address to probe
253 *
254 * Returns true if PHY found
255 */
ixgbe_probe_phy(struct ixgbe_hw * hw,u16 phy_addr)256 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
257 {
258 u16 ext_ability = 0;
259
260 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
261 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
262 phy_addr);
263 return false;
264 }
265
266 if (ixgbe_get_phy_id(hw))
267 return false;
268
269 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
270
271 if (hw->phy.type == ixgbe_phy_unknown) {
272 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
273 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
274 if (ext_ability &
275 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
276 IXGBE_MDIO_PHY_1000BASET_ABILITY))
277 hw->phy.type = ixgbe_phy_cu_unknown;
278 else
279 hw->phy.type = ixgbe_phy_generic;
280 }
281
282 return true;
283 }
284
285 /**
286 * ixgbe_identify_phy_generic - Get physical layer module
287 * @hw: pointer to hardware structure
288 *
289 * Determines the physical layer module found on the current adapter.
290 **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)291 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
292 {
293 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
294 u16 phy_addr;
295
296 DEBUGFUNC("ixgbe_identify_phy_generic");
297
298 if (!hw->phy.phy_semaphore_mask) {
299 if (hw->bus.lan_id)
300 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
301 else
302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
303 }
304
305 if (hw->phy.type != ixgbe_phy_unknown)
306 return IXGBE_SUCCESS;
307
308 if (hw->phy.nw_mng_if_sel) {
309 phy_addr = (hw->phy.nw_mng_if_sel &
310 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
311 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
312 if (ixgbe_probe_phy(hw, phy_addr))
313 return IXGBE_SUCCESS;
314 else
315 return IXGBE_ERR_PHY_ADDR_INVALID;
316 }
317
318 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
319 if (ixgbe_probe_phy(hw, phy_addr)) {
320 status = IXGBE_SUCCESS;
321 break;
322 }
323 }
324
325 /* Certain media types do not have a phy so an address will not
326 * be found and the code will take this path. Caller has to
327 * decide if it is an error or not.
328 */
329 if (status != IXGBE_SUCCESS)
330 hw->phy.addr = 0;
331
332 return status;
333 }
334
335 /**
336 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
337 * @hw: pointer to the hardware structure
338 *
339 * This function checks the MMNGC.MNG_VETO bit to see if there are
340 * any constraints on link from manageability. For MAC's that don't
341 * have this bit just return faluse since the link can not be blocked
342 * via this method.
343 **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)344 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
345 {
346 u32 mmngc;
347
348 DEBUGFUNC("ixgbe_check_reset_blocked");
349
350 /* If we don't have this bit, it can't be blocking */
351 if (hw->mac.type == ixgbe_mac_82598EB)
352 return false;
353
354 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
355 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
356 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
357 "MNG_VETO bit detected.\n");
358 return true;
359 }
360
361 return false;
362 }
363
364 /**
365 * ixgbe_validate_phy_addr - Determines phy address is valid
366 * @hw: pointer to hardware structure
367 * @phy_addr: PHY address
368 *
369 **/
ixgbe_validate_phy_addr(struct ixgbe_hw * hw,u32 phy_addr)370 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
371 {
372 u16 phy_id = 0;
373 bool valid = false;
374
375 DEBUGFUNC("ixgbe_validate_phy_addr");
376
377 hw->phy.addr = phy_addr;
378 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
379 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
380
381 if (phy_id != 0xFFFF && phy_id != 0x0)
382 valid = true;
383
384 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
385
386 return valid;
387 }
388
389 /**
390 * ixgbe_get_phy_id - Get the phy type
391 * @hw: pointer to hardware structure
392 *
393 **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)394 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
395 {
396 u32 status;
397 u16 phy_id_high = 0;
398 u16 phy_id_low = 0;
399
400 DEBUGFUNC("ixgbe_get_phy_id");
401
402 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
403 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
404 &phy_id_high);
405
406 if (status == IXGBE_SUCCESS) {
407 hw->phy.id = (u32)(phy_id_high << 16);
408 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
409 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
410 &phy_id_low);
411 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
412 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
413 }
414 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
415 phy_id_high, phy_id_low);
416
417 return status;
418 }
419
420 /**
421 * ixgbe_get_phy_type_from_id - Get the phy type
422 * @phy_id: PHY ID information
423 *
424 **/
ixgbe_get_phy_type_from_id(u32 phy_id)425 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
426 {
427 enum ixgbe_phy_type phy_type;
428
429 DEBUGFUNC("ixgbe_get_phy_type_from_id");
430
431 switch (phy_id) {
432 case TN1010_PHY_ID:
433 phy_type = ixgbe_phy_tn;
434 break;
435 case X550_PHY_ID2:
436 case X550_PHY_ID3:
437 case X540_PHY_ID:
438 phy_type = ixgbe_phy_aq;
439 break;
440 case QT2022_PHY_ID:
441 phy_type = ixgbe_phy_qt;
442 break;
443 case ATH_PHY_ID:
444 phy_type = ixgbe_phy_nl;
445 break;
446 case X557_PHY_ID:
447 case X557_PHY_ID2:
448 phy_type = ixgbe_phy_x550em_ext_t;
449 break;
450 case IXGBE_M88E1500_E_PHY_ID:
451 case IXGBE_M88E1543_E_PHY_ID:
452 phy_type = ixgbe_phy_ext_1g_t;
453 break;
454 default:
455 phy_type = ixgbe_phy_unknown;
456 break;
457 }
458 return phy_type;
459 }
460
461 /**
462 * ixgbe_reset_phy_generic - Performs a PHY reset
463 * @hw: pointer to hardware structure
464 **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)465 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
466 {
467 u32 i;
468 u16 ctrl = 0;
469 s32 status = IXGBE_SUCCESS;
470
471 DEBUGFUNC("ixgbe_reset_phy_generic");
472
473 if (hw->phy.type == ixgbe_phy_unknown)
474 status = ixgbe_identify_phy_generic(hw);
475
476 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
477 goto out;
478
479 /* Don't reset PHY if it's shut down due to overtemp. */
480 if (!hw->phy.reset_if_overtemp &&
481 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
482 goto out;
483
484 /* Blocked by MNG FW so bail */
485 if (ixgbe_check_reset_blocked(hw))
486 goto out;
487
488 /*
489 * Perform soft PHY reset to the PHY_XS.
490 * This will cause a soft reset to the PHY
491 */
492 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
493 IXGBE_MDIO_PHY_XS_DEV_TYPE,
494 IXGBE_MDIO_PHY_XS_RESET);
495
496 /*
497 * Poll for reset bit to self-clear indicating reset is complete.
498 * Some PHYs could take up to 3 seconds to complete and need about
499 * 1.7 usec delay after the reset is complete.
500 */
501 for (i = 0; i < 30; i++) {
502 msec_delay(100);
503 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
504 status = hw->phy.ops.read_reg(hw,
505 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
506 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
507 &ctrl);
508 if (status != IXGBE_SUCCESS)
509 return status;
510
511 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
512 usec_delay(2);
513 break;
514 }
515 } else {
516 status = hw->phy.ops.read_reg(hw,
517 IXGBE_MDIO_PHY_XS_CONTROL,
518 IXGBE_MDIO_PHY_XS_DEV_TYPE,
519 &ctrl);
520 if (status != IXGBE_SUCCESS)
521 return status;
522
523 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
524 usec_delay(2);
525 break;
526 }
527 }
528 }
529
530 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
531 status = IXGBE_ERR_RESET_FAILED;
532 ERROR_REPORT1(IXGBE_ERROR_POLLING,
533 "PHY reset polling failed to complete.\n");
534 }
535
536 out:
537 return status;
538 }
539
540 /**
541 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
542 * @hw: pointer to hardware structure
543 **/
ixgbe_restart_auto_neg(struct ixgbe_hw * hw)544 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
545 {
546 u16 autoneg_reg;
547
548 /* Check if PHY reset is blocked by MNG FW */
549 if (ixgbe_check_reset_blocked(hw))
550 return;
551
552 /* Restart PHY auto-negotiation. */
553 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
554 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
555 autoneg_reg |= IXGBE_MII_RESTART;
556 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
557 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
558 }
559
560 /**
561 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
562 * the SWFW lock
563 * @hw: pointer to hardware structure
564 * @reg_addr: 32 bit address of PHY register to read
565 * @device_type: 5 bit device type
566 * @phy_data: Pointer to read data from PHY register
567 **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)568 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
569 u16 *phy_data)
570 {
571 u32 i, data, command;
572
573 /* Setup and write the address cycle command */
574 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
575 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
576 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
577 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
578
579 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
580
581 /*
582 * Check every 10 usec to see if the address cycle completed.
583 * The MDI Command bit will clear when the operation is
584 * complete
585 */
586 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
587 usec_delay(10);
588
589 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
590 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
591 break;
592 }
593
594
595 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
596 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
597 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
598 return IXGBE_ERR_PHY;
599 }
600
601 /*
602 * Address cycle complete, setup and write the read
603 * command
604 */
605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
608 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
609
610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
611
612 /*
613 * Check every 10 usec to see if the address cycle
614 * completed. The MDI Command bit will clear when the
615 * operation is complete
616 */
617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
618 usec_delay(10);
619
620 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
622 break;
623 }
624
625 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
626 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
627 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
628 return IXGBE_ERR_PHY;
629 }
630
631 /*
632 * Read operation is complete. Get the data
633 * from MSRWD
634 */
635 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
636 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
637 *phy_data = (u16)(data);
638
639 return IXGBE_SUCCESS;
640 }
641
642 /**
643 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
644 * using the SWFW lock - this function is needed in most cases
645 * @hw: pointer to hardware structure
646 * @reg_addr: 32 bit address of PHY register to read
647 * @device_type: 5 bit device type
648 * @phy_data: Pointer to read data from PHY register
649 **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)650 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
651 u32 device_type, u16 *phy_data)
652 {
653 s32 status;
654 u32 gssr = hw->phy.phy_semaphore_mask;
655
656 DEBUGFUNC("ixgbe_read_phy_reg_generic");
657
658 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
659 return IXGBE_ERR_SWFW_SYNC;
660
661 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
662
663 hw->mac.ops.release_swfw_sync(hw, gssr);
664
665 return status;
666 }
667
668 /**
669 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
670 * without SWFW lock
671 * @hw: pointer to hardware structure
672 * @reg_addr: 32 bit PHY register to write
673 * @device_type: 5 bit device type
674 * @phy_data: Data to write to the PHY register
675 **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)676 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
677 u32 device_type, u16 phy_data)
678 {
679 u32 i, command;
680
681 /* Put the data in the MDI single read and write data register*/
682 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
683
684 /* Setup and write the address cycle command */
685 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
686 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
687 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
688 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
689
690 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
691
692 /*
693 * Check every 10 usec to see if the address cycle completed.
694 * The MDI Command bit will clear when the operation is
695 * complete
696 */
697 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
698 usec_delay(10);
699
700 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
701 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
702 break;
703 }
704
705 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
706 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
707 return IXGBE_ERR_PHY;
708 }
709
710 /*
711 * Address cycle complete, setup and write the write
712 * command
713 */
714 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
715 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
716 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
717 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
718
719 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
720
721 /*
722 * Check every 10 usec to see if the address cycle
723 * completed. The MDI Command bit will clear when the
724 * operation is complete
725 */
726 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
727 usec_delay(10);
728
729 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
730 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
731 break;
732 }
733
734 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
735 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
736 return IXGBE_ERR_PHY;
737 }
738
739 return IXGBE_SUCCESS;
740 }
741
742 /**
743 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
744 * using SWFW lock- this function is needed in most cases
745 * @hw: pointer to hardware structure
746 * @reg_addr: 32 bit PHY register to write
747 * @device_type: 5 bit device type
748 * @phy_data: Data to write to the PHY register
749 **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)750 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
751 u32 device_type, u16 phy_data)
752 {
753 s32 status;
754 u32 gssr = hw->phy.phy_semaphore_mask;
755
756 DEBUGFUNC("ixgbe_write_phy_reg_generic");
757
758 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
759 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
760 phy_data);
761 hw->mac.ops.release_swfw_sync(hw, gssr);
762 } else {
763 status = IXGBE_ERR_SWFW_SYNC;
764 }
765
766 return status;
767 }
768
769 /**
770 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
771 * @hw: pointer to hardware structure
772 *
773 * Restart auto-negotiation and PHY and waits for completion.
774 **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)775 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
776 {
777 s32 status = IXGBE_SUCCESS;
778 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
779 bool autoneg = false;
780 ixgbe_link_speed speed;
781
782 DEBUGFUNC("ixgbe_setup_phy_link_generic");
783
784 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
785
786 /* Set or unset auto-negotiation 10G advertisement */
787 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
788 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
789 &autoneg_reg);
790
791 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
792 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
793 (speed & IXGBE_LINK_SPEED_10GB_FULL))
794 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
795
796 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
797 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
798 autoneg_reg);
799
800 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
802 &autoneg_reg);
803
804 if (hw->mac.type == ixgbe_mac_X550) {
805 /* Set or unset auto-negotiation 5G advertisement */
806 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
807 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
808 (speed & IXGBE_LINK_SPEED_5GB_FULL))
809 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
810
811 /* Set or unset auto-negotiation 2.5G advertisement */
812 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
813 if ((hw->phy.autoneg_advertised &
814 IXGBE_LINK_SPEED_2_5GB_FULL) &&
815 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
816 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
817 }
818
819 /* Set or unset auto-negotiation 1G advertisement */
820 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
822 (speed & IXGBE_LINK_SPEED_1GB_FULL))
823 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
824
825 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
827 autoneg_reg);
828
829 /* Set or unset auto-negotiation 100M advertisement */
830 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
831 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
832 &autoneg_reg);
833
834 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
835 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
836 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
837 (speed & IXGBE_LINK_SPEED_100_FULL))
838 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
839
840 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
841 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
842 autoneg_reg);
843
844 ixgbe_restart_auto_neg(hw);
845 return status;
846 }
847
848 /**
849 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
850 * @hw: pointer to hardware structure
851 * @speed: new link speed
852 * @autoneg_wait_to_complete: unused
853 **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)854 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
855 ixgbe_link_speed speed,
856 bool autoneg_wait_to_complete)
857 {
858 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
859
860 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
861
862 /*
863 * Clear autoneg_advertised and set new values based on input link
864 * speed.
865 */
866 hw->phy.autoneg_advertised = 0;
867
868 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
869 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
870
871 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
872 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
873
874 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
875 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
876
877 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
878 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
879
880 if (speed & IXGBE_LINK_SPEED_100_FULL)
881 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
882
883 if (speed & IXGBE_LINK_SPEED_10_FULL)
884 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
885
886 /* Setup link based on the new speed settings */
887 ixgbe_setup_phy_link(hw);
888
889 return IXGBE_SUCCESS;
890 }
891
892 /**
893 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
894 * @hw: pointer to hardware structure
895 *
896 * Determines the supported link capabilities by reading the PHY auto
897 * negotiation register.
898 **/
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)899 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
900 {
901 s32 status;
902 u16 speed_ability;
903
904 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
905 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
906 &speed_ability);
907 if (status)
908 return status;
909
910 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
911 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
912 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
913 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
914 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
915 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
916
917 switch (hw->mac.type) {
918 case ixgbe_mac_X550EM_x:
919 case ixgbe_mac_X550EM_a:
920 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
921 break;
922 default:
923 break;
924 }
925
926 return status;
927 }
928
929 /**
930 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
931 * @hw: pointer to hardware structure
932 * @speed: pointer to link speed
933 * @autoneg: boolean auto-negotiation value
934 **/
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)935 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
936 ixgbe_link_speed *speed,
937 bool *autoneg)
938 {
939 s32 status = IXGBE_SUCCESS;
940
941 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
942
943 *autoneg = true;
944 if (!hw->phy.speeds_supported)
945 status = ixgbe_get_copper_speeds_supported(hw);
946
947 *speed = hw->phy.speeds_supported;
948 return status;
949 }
950
951 /**
952 * ixgbe_check_phy_link_tnx - Determine link and speed status
953 * @hw: pointer to hardware structure
954 * @speed: current link speed
955 * @link_up: true is link is up, false otherwise
956 *
957 * Reads the VS1 register to determine if link is up and the current speed for
958 * the PHY.
959 **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)960 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
961 bool *link_up)
962 {
963 s32 status = IXGBE_SUCCESS;
964 u32 time_out;
965 u32 max_time_out = 10;
966 u16 phy_link = 0;
967 u16 phy_speed = 0;
968 u16 phy_data = 0;
969
970 DEBUGFUNC("ixgbe_check_phy_link_tnx");
971
972 /* Initialize speed and link to default case */
973 *link_up = false;
974 *speed = IXGBE_LINK_SPEED_10GB_FULL;
975
976 /*
977 * Check current speed and link status of the PHY register.
978 * This is a vendor specific register and may have to
979 * be changed for other copper PHYs.
980 */
981 for (time_out = 0; time_out < max_time_out; time_out++) {
982 usec_delay(10);
983 status = hw->phy.ops.read_reg(hw,
984 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
985 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
986 &phy_data);
987 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
988 phy_speed = phy_data &
989 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
990 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
991 *link_up = true;
992 if (phy_speed ==
993 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
994 *speed = IXGBE_LINK_SPEED_1GB_FULL;
995 break;
996 }
997 }
998
999 return status;
1000 }
1001
1002 /**
1003 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1004 * @hw: pointer to hardware structure
1005 *
1006 * Restart auto-negotiation and PHY and waits for completion.
1007 **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)1008 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1009 {
1010 s32 status = IXGBE_SUCCESS;
1011 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1012 bool autoneg = false;
1013 ixgbe_link_speed speed;
1014
1015 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1016
1017 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1018
1019 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1020 /* Set or unset auto-negotiation 10G advertisement */
1021 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1022 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1023 &autoneg_reg);
1024
1025 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1026 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1027 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1028
1029 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1030 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1031 autoneg_reg);
1032 }
1033
1034 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1035 /* Set or unset auto-negotiation 1G advertisement */
1036 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1037 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1038 &autoneg_reg);
1039
1040 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1041 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1042 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1043
1044 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1045 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1046 autoneg_reg);
1047 }
1048
1049 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1050 /* Set or unset auto-negotiation 100M advertisement */
1051 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1052 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1053 &autoneg_reg);
1054
1055 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1056 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1057 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1058
1059 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1060 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1061 autoneg_reg);
1062 }
1063
1064 ixgbe_restart_auto_neg(hw);
1065 return status;
1066 }
1067
1068 /**
1069 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1070 * @hw: pointer to hardware structure
1071 * @firmware_version: pointer to the PHY Firmware Version
1072 **/
ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw * hw,u16 * firmware_version)1073 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1074 u16 *firmware_version)
1075 {
1076 s32 status;
1077
1078 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1079
1080 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1081 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1082 firmware_version);
1083
1084 return status;
1085 }
1086
1087 /**
1088 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1089 * @hw: pointer to hardware structure
1090 * @firmware_version: pointer to the PHY Firmware Version
1091 **/
ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw * hw,u16 * firmware_version)1092 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1093 u16 *firmware_version)
1094 {
1095 s32 status;
1096
1097 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1098
1099 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1100 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1101 firmware_version);
1102
1103 return status;
1104 }
1105
1106 /**
1107 * ixgbe_reset_phy_nl - Performs a PHY reset
1108 * @hw: pointer to hardware structure
1109 **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1110 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1111 {
1112 u16 phy_offset, control, eword, edata, block_crc;
1113 bool end_data = false;
1114 u16 list_offset, data_offset;
1115 u16 phy_data = 0;
1116 s32 ret_val = IXGBE_SUCCESS;
1117 u32 i;
1118
1119 DEBUGFUNC("ixgbe_reset_phy_nl");
1120
1121 /* Blocked by MNG FW so bail */
1122 if (ixgbe_check_reset_blocked(hw))
1123 goto out;
1124
1125 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1126 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1127
1128 /* reset the PHY and poll for completion */
1129 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1130 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1131 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1132
1133 for (i = 0; i < 100; i++) {
1134 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1135 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1136 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1137 break;
1138 msec_delay(10);
1139 }
1140
1141 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1142 DEBUGOUT("PHY reset did not complete.\n");
1143 ret_val = IXGBE_ERR_PHY;
1144 goto out;
1145 }
1146
1147 /* Get init offsets */
1148 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1149 &data_offset);
1150 if (ret_val != IXGBE_SUCCESS)
1151 goto out;
1152
1153 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1154 data_offset++;
1155 while (!end_data) {
1156 /*
1157 * Read control word from PHY init contents offset
1158 */
1159 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1160 if (ret_val)
1161 goto err_eeprom;
1162 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1163 IXGBE_CONTROL_SHIFT_NL;
1164 edata = eword & IXGBE_DATA_MASK_NL;
1165 switch (control) {
1166 case IXGBE_DELAY_NL:
1167 data_offset++;
1168 DEBUGOUT1("DELAY: %d MS\n", edata);
1169 msec_delay(edata);
1170 break;
1171 case IXGBE_DATA_NL:
1172 DEBUGOUT("DATA:\n");
1173 data_offset++;
1174 ret_val = hw->eeprom.ops.read(hw, data_offset,
1175 &phy_offset);
1176 if (ret_val)
1177 goto err_eeprom;
1178 data_offset++;
1179 for (i = 0; i < edata; i++) {
1180 ret_val = hw->eeprom.ops.read(hw, data_offset,
1181 &eword);
1182 if (ret_val)
1183 goto err_eeprom;
1184 hw->phy.ops.write_reg(hw, phy_offset,
1185 IXGBE_TWINAX_DEV, eword);
1186 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1187 phy_offset);
1188 data_offset++;
1189 phy_offset++;
1190 }
1191 break;
1192 case IXGBE_CONTROL_NL:
1193 data_offset++;
1194 DEBUGOUT("CONTROL:\n");
1195 if (edata == IXGBE_CONTROL_EOL_NL) {
1196 DEBUGOUT("EOL\n");
1197 end_data = true;
1198 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1199 DEBUGOUT("SOL\n");
1200 } else {
1201 DEBUGOUT("Bad control value\n");
1202 ret_val = IXGBE_ERR_PHY;
1203 goto out;
1204 }
1205 break;
1206 default:
1207 DEBUGOUT("Bad control type\n");
1208 ret_val = IXGBE_ERR_PHY;
1209 goto out;
1210 }
1211 }
1212
1213 out:
1214 return ret_val;
1215
1216 err_eeprom:
1217 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1218 "eeprom read at offset %d failed", data_offset);
1219 return IXGBE_ERR_PHY;
1220 }
1221
1222 /**
1223 * ixgbe_identify_module_generic - Identifies module type
1224 * @hw: pointer to hardware structure
1225 *
1226 * Determines HW type and calls appropriate function.
1227 **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1228 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1229 {
1230 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1231
1232 DEBUGFUNC("ixgbe_identify_module_generic");
1233
1234 switch (hw->mac.ops.get_media_type(hw)) {
1235 case ixgbe_media_type_fiber:
1236 status = ixgbe_identify_sfp_module_generic(hw);
1237 break;
1238
1239 case ixgbe_media_type_fiber_qsfp:
1240 status = ixgbe_identify_qsfp_module_generic(hw);
1241 break;
1242
1243 default:
1244 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1245 status = IXGBE_ERR_SFP_NOT_PRESENT;
1246 break;
1247 }
1248
1249 return status;
1250 }
1251
1252 /**
1253 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1254 * @hw: pointer to hardware structure
1255 *
1256 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1257 **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1258 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1259 {
1260 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1261 u32 vendor_oui = 0;
1262 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1263 u8 identifier = 0;
1264 u8 comp_codes_1g = 0;
1265 u8 comp_codes_10g = 0;
1266 u8 oui_bytes[3] = {0, 0, 0};
1267 u8 cable_tech = 0;
1268 u8 cable_spec = 0;
1269 u16 enforce_sfp = 0;
1270 u8 retries;
1271
1272 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1273
1274 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1275 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1276 status = IXGBE_ERR_SFP_NOT_PRESENT;
1277 goto out;
1278 }
1279
1280 /* LAN ID is needed for I2C access */
1281 hw->mac.ops.set_lan_id(hw);
1282
1283 /* Need to check this a couple of times for a sane value.
1284 *
1285 * SFPs that have a uC slaved to the I2C bus (vs. a dumb EEPROM) can be
1286 * poorly designed such that they will ACK I2C reads and return
1287 * whatever bogus data is in the SRAM (or whatever is backing the target
1288 * device) before things are truly initialized.
1289 *
1290 * In a perfect world devices would NAK I2C requests until they were
1291 * sane, but here we are.
1292 *
1293 * Give such devices a couple tries to get their act together before
1294 * marking the device as unsupported.
1295 */
1296 for (retries = 0; retries < 5; retries++) {
1297 status = hw->phy.ops.read_i2c_eeprom(hw,
1298 IXGBE_SFF_IDENTIFIER,
1299 &identifier);
1300
1301 DEBUGOUT("status %d, SFF identifier 0x%x\n", status, identifier);
1302 if (status == IXGBE_SUCCESS &&
1303 identifier == IXGBE_SFF_IDENTIFIER_SFP)
1304 break;
1305 }
1306
1307 if (status != IXGBE_SUCCESS)
1308 goto err_read_i2c_eeprom;
1309
1310 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1311 hw->phy.type = ixgbe_phy_sfp_unsupported;
1312 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1313 } else {
1314 status = hw->phy.ops.read_i2c_eeprom(hw,
1315 IXGBE_SFF_1GBE_COMP_CODES,
1316 &comp_codes_1g);
1317
1318 if (status != IXGBE_SUCCESS)
1319 goto err_read_i2c_eeprom;
1320
1321 status = hw->phy.ops.read_i2c_eeprom(hw,
1322 IXGBE_SFF_10GBE_COMP_CODES,
1323 &comp_codes_10g);
1324
1325 if (status != IXGBE_SUCCESS)
1326 goto err_read_i2c_eeprom;
1327 status = hw->phy.ops.read_i2c_eeprom(hw,
1328 IXGBE_SFF_CABLE_TECHNOLOGY,
1329 &cable_tech);
1330
1331 if (status != IXGBE_SUCCESS)
1332 goto err_read_i2c_eeprom;
1333
1334 /* ID Module
1335 * =========
1336 * 0 SFP_DA_CU
1337 * 1 SFP_SR
1338 * 2 SFP_LR
1339 * 3 SFP_DA_CORE0 - 82599-specific
1340 * 4 SFP_DA_CORE1 - 82599-specific
1341 * 5 SFP_SR/LR_CORE0 - 82599-specific
1342 * 6 SFP_SR/LR_CORE1 - 82599-specific
1343 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1344 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1345 * 9 SFP_1g_cu_CORE0 - 82599-specific
1346 * 10 SFP_1g_cu_CORE1 - 82599-specific
1347 * 11 SFP_1g_sx_CORE0 - 82599-specific
1348 * 12 SFP_1g_sx_CORE1 - 82599-specific
1349 */
1350 if (hw->mac.type == ixgbe_mac_82598EB) {
1351 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1352 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1353 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1354 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1355 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1356 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1357 else
1358 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1359 } else {
1360 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1361 if (hw->bus.lan_id == 0)
1362 hw->phy.sfp_type =
1363 ixgbe_sfp_type_da_cu_core0;
1364 else
1365 hw->phy.sfp_type =
1366 ixgbe_sfp_type_da_cu_core1;
1367 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1368 hw->phy.ops.read_i2c_eeprom(
1369 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1370 &cable_spec);
1371 if (cable_spec &
1372 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1373 if (hw->bus.lan_id == 0)
1374 hw->phy.sfp_type =
1375 ixgbe_sfp_type_da_act_lmt_core0;
1376 else
1377 hw->phy.sfp_type =
1378 ixgbe_sfp_type_da_act_lmt_core1;
1379 } else {
1380 hw->phy.sfp_type =
1381 ixgbe_sfp_type_unknown;
1382 }
1383 } else if (comp_codes_10g &
1384 (IXGBE_SFF_10GBASESR_CAPABLE |
1385 IXGBE_SFF_10GBASELR_CAPABLE)) {
1386 if (hw->bus.lan_id == 0)
1387 hw->phy.sfp_type =
1388 ixgbe_sfp_type_srlr_core0;
1389 else
1390 hw->phy.sfp_type =
1391 ixgbe_sfp_type_srlr_core1;
1392 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1393 if (hw->bus.lan_id == 0)
1394 hw->phy.sfp_type =
1395 ixgbe_sfp_type_1g_cu_core0;
1396 else
1397 hw->phy.sfp_type =
1398 ixgbe_sfp_type_1g_cu_core1;
1399 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1400 if (hw->bus.lan_id == 0)
1401 hw->phy.sfp_type =
1402 ixgbe_sfp_type_1g_sx_core0;
1403 else
1404 hw->phy.sfp_type =
1405 ixgbe_sfp_type_1g_sx_core1;
1406 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1407 if (hw->bus.lan_id == 0)
1408 hw->phy.sfp_type =
1409 ixgbe_sfp_type_1g_lx_core0;
1410 else
1411 hw->phy.sfp_type =
1412 ixgbe_sfp_type_1g_lx_core1;
1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASELHA_CAPABLE) {
1414 if (hw->bus.lan_id == 0)
1415 hw->phy.sfp_type =
1416 ixgbe_sfp_type_1g_lha_core0;
1417 else
1418 hw->phy.sfp_type =
1419 ixgbe_sfp_type_1g_lha_core1;
1420 } else {
1421 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1422 }
1423 }
1424
1425 if (hw->phy.sfp_type != stored_sfp_type)
1426 hw->phy.sfp_setup_needed = true;
1427
1428 /* Determine if the SFP+ PHY is dual speed or not. */
1429 hw->phy.multispeed_fiber = false;
1430 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1431 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1432 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1433 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1434 hw->phy.multispeed_fiber = true;
1435
1436 /* Determine PHY vendor */
1437 if (hw->phy.type != ixgbe_phy_nl) {
1438 hw->phy.id = identifier;
1439 status = hw->phy.ops.read_i2c_eeprom(hw,
1440 IXGBE_SFF_VENDOR_OUI_BYTE0,
1441 &oui_bytes[0]);
1442
1443 if (status != IXGBE_SUCCESS)
1444 goto err_read_i2c_eeprom;
1445
1446 status = hw->phy.ops.read_i2c_eeprom(hw,
1447 IXGBE_SFF_VENDOR_OUI_BYTE1,
1448 &oui_bytes[1]);
1449
1450 if (status != IXGBE_SUCCESS)
1451 goto err_read_i2c_eeprom;
1452
1453 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 IXGBE_SFF_VENDOR_OUI_BYTE2,
1455 &oui_bytes[2]);
1456
1457 if (status != IXGBE_SUCCESS)
1458 goto err_read_i2c_eeprom;
1459
1460 vendor_oui =
1461 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1462 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1463 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1464
1465 switch (vendor_oui) {
1466 case IXGBE_SFF_VENDOR_OUI_TYCO:
1467 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1468 hw->phy.type =
1469 ixgbe_phy_sfp_passive_tyco;
1470 break;
1471 case IXGBE_SFF_VENDOR_OUI_FTL:
1472 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1473 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1474 else
1475 hw->phy.type = ixgbe_phy_sfp_ftl;
1476 break;
1477 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1478 hw->phy.type = ixgbe_phy_sfp_avago;
1479 break;
1480 case IXGBE_SFF_VENDOR_OUI_INTEL:
1481 hw->phy.type = ixgbe_phy_sfp_intel;
1482 break;
1483 default:
1484 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1485 hw->phy.type =
1486 ixgbe_phy_sfp_passive_unknown;
1487 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1488 hw->phy.type =
1489 ixgbe_phy_sfp_active_unknown;
1490 else
1491 hw->phy.type = ixgbe_phy_sfp_unknown;
1492 break;
1493 }
1494 }
1495
1496 /* Allow any DA cable vendor */
1497 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1498 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1499 status = IXGBE_SUCCESS;
1500 goto out;
1501 }
1502
1503 /* Verify supported 1G SFP modules */
1504 if (comp_codes_10g == 0 &&
1505 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1506 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1507 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1508 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1509 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1510 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1513 hw->phy.type = ixgbe_phy_sfp_unsupported;
1514 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1515 goto out;
1516 }
1517
1518 /* Anything else 82598-based is supported */
1519 if (hw->mac.type == ixgbe_mac_82598EB) {
1520 status = IXGBE_SUCCESS;
1521 goto out;
1522 }
1523
1524 ixgbe_get_device_caps(hw, &enforce_sfp);
1525 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1526 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1527 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1528 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1529 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1534 /* Make sure we're a supported PHY type */
1535 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1536 status = IXGBE_SUCCESS;
1537 } else {
1538 if (hw->allow_unsupported_sfp == true) {
1539 EWARN(hw,
1540 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1541 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1542 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1543 status = IXGBE_SUCCESS;
1544 } else {
1545 DEBUGOUT("SFP+ module not supported\n");
1546 hw->phy.type =
1547 ixgbe_phy_sfp_unsupported;
1548 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1549 }
1550 }
1551 } else {
1552 status = IXGBE_SUCCESS;
1553 }
1554 }
1555
1556 out:
1557 return status;
1558
1559 err_read_i2c_eeprom:
1560 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1561 if (hw->phy.type != ixgbe_phy_nl) {
1562 hw->phy.id = 0;
1563 hw->phy.type = ixgbe_phy_unknown;
1564 }
1565 return IXGBE_ERR_SFP_NOT_PRESENT;
1566 }
1567
1568 /**
1569 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1570 * @hw: pointer to hardware structure
1571 *
1572 * Determines physical layer capabilities of the current SFP.
1573 */
ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw * hw)1574 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1575 {
1576 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1577 u8 comp_codes_10g = 0;
1578 u8 comp_codes_1g = 0;
1579
1580 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1581
1582 hw->phy.ops.identify_sfp(hw);
1583 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1584 return physical_layer;
1585
1586 switch (hw->phy.type) {
1587 case ixgbe_phy_sfp_passive_tyco:
1588 case ixgbe_phy_sfp_passive_unknown:
1589 case ixgbe_phy_qsfp_passive_unknown:
1590 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1591 break;
1592 case ixgbe_phy_sfp_ftl_active:
1593 case ixgbe_phy_sfp_active_unknown:
1594 case ixgbe_phy_qsfp_active_unknown:
1595 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1596 break;
1597 case ixgbe_phy_sfp_avago:
1598 case ixgbe_phy_sfp_ftl:
1599 case ixgbe_phy_sfp_intel:
1600 case ixgbe_phy_sfp_unknown:
1601 hw->phy.ops.read_i2c_eeprom(hw,
1602 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1603 hw->phy.ops.read_i2c_eeprom(hw,
1604 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1605 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1606 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1607 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1608 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1609 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1610 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1611 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1612 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1613 break;
1614 case ixgbe_phy_qsfp_intel:
1615 case ixgbe_phy_qsfp_unknown:
1616 hw->phy.ops.read_i2c_eeprom(hw,
1617 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1618 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1619 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1620 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1621 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1622 break;
1623 default:
1624 break;
1625 }
1626
1627 return physical_layer;
1628 }
1629
1630 /**
1631 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1632 * @hw: pointer to hardware structure
1633 *
1634 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1635 **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1636 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1637 {
1638 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1639 u32 vendor_oui = 0;
1640 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1641 u8 identifier = 0;
1642 u8 comp_codes_1g = 0;
1643 u8 comp_codes_10g = 0;
1644 u8 oui_bytes[3] = {0, 0, 0};
1645 u16 enforce_sfp = 0;
1646 u8 connector = 0;
1647 u8 cable_length = 0;
1648 u8 device_tech = 0;
1649 bool active_cable = false;
1650
1651 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1652
1653 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1654 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1655 status = IXGBE_ERR_SFP_NOT_PRESENT;
1656 goto out;
1657 }
1658
1659 /* LAN ID is needed for I2C access */
1660 hw->mac.ops.set_lan_id(hw);
1661
1662 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1663 &identifier);
1664
1665 if (status != IXGBE_SUCCESS)
1666 goto err_read_i2c_eeprom;
1667
1668 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1669 hw->phy.type = ixgbe_phy_sfp_unsupported;
1670 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1671 goto out;
1672 }
1673
1674 hw->phy.id = identifier;
1675
1676 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1677 &comp_codes_10g);
1678
1679 if (status != IXGBE_SUCCESS)
1680 goto err_read_i2c_eeprom;
1681
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1683 &comp_codes_1g);
1684
1685 if (status != IXGBE_SUCCESS)
1686 goto err_read_i2c_eeprom;
1687
1688 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1689 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1690 if (hw->bus.lan_id == 0)
1691 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1692 else
1693 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1694 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1695 IXGBE_SFF_10GBASELR_CAPABLE)) {
1696 if (hw->bus.lan_id == 0)
1697 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1698 else
1699 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1700 } else {
1701 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1702 active_cable = true;
1703
1704 if (!active_cable) {
1705 /* check for active DA cables that pre-date
1706 * SFF-8436 v3.6 */
1707 hw->phy.ops.read_i2c_eeprom(hw,
1708 IXGBE_SFF_QSFP_CONNECTOR,
1709 &connector);
1710
1711 hw->phy.ops.read_i2c_eeprom(hw,
1712 IXGBE_SFF_QSFP_CABLE_LENGTH,
1713 &cable_length);
1714
1715 hw->phy.ops.read_i2c_eeprom(hw,
1716 IXGBE_SFF_QSFP_DEVICE_TECH,
1717 &device_tech);
1718
1719 if ((connector ==
1720 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1721 (cable_length > 0) &&
1722 ((device_tech >> 4) ==
1723 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1724 active_cable = true;
1725 }
1726
1727 if (active_cable) {
1728 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1729 if (hw->bus.lan_id == 0)
1730 hw->phy.sfp_type =
1731 ixgbe_sfp_type_da_act_lmt_core0;
1732 else
1733 hw->phy.sfp_type =
1734 ixgbe_sfp_type_da_act_lmt_core1;
1735 } else {
1736 /* unsupported module type */
1737 hw->phy.type = ixgbe_phy_sfp_unsupported;
1738 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1739 goto out;
1740 }
1741 }
1742
1743 if (hw->phy.sfp_type != stored_sfp_type)
1744 hw->phy.sfp_setup_needed = true;
1745
1746 /* Determine if the QSFP+ PHY is dual speed or not. */
1747 hw->phy.multispeed_fiber = false;
1748 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1749 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1750 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1751 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1752 hw->phy.multispeed_fiber = true;
1753
1754 /* Determine PHY vendor for optical modules */
1755 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1756 IXGBE_SFF_10GBASELR_CAPABLE)) {
1757 status = hw->phy.ops.read_i2c_eeprom(hw,
1758 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1759 &oui_bytes[0]);
1760
1761 if (status != IXGBE_SUCCESS)
1762 goto err_read_i2c_eeprom;
1763
1764 status = hw->phy.ops.read_i2c_eeprom(hw,
1765 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1766 &oui_bytes[1]);
1767
1768 if (status != IXGBE_SUCCESS)
1769 goto err_read_i2c_eeprom;
1770
1771 status = hw->phy.ops.read_i2c_eeprom(hw,
1772 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1773 &oui_bytes[2]);
1774
1775 if (status != IXGBE_SUCCESS)
1776 goto err_read_i2c_eeprom;
1777
1778 vendor_oui =
1779 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1780 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1781 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1782
1783 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1784 hw->phy.type = ixgbe_phy_qsfp_intel;
1785 else
1786 hw->phy.type = ixgbe_phy_qsfp_unknown;
1787
1788 ixgbe_get_device_caps(hw, &enforce_sfp);
1789 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1790 /* Make sure we're a supported PHY type */
1791 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1792 status = IXGBE_SUCCESS;
1793 } else {
1794 if (hw->allow_unsupported_sfp == true) {
1795 EWARN(hw,
1796 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1797 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1798 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1799 status = IXGBE_SUCCESS;
1800 } else {
1801 DEBUGOUT("QSFP module not supported\n");
1802 hw->phy.type =
1803 ixgbe_phy_sfp_unsupported;
1804 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1805 }
1806 }
1807 } else {
1808 status = IXGBE_SUCCESS;
1809 }
1810 }
1811
1812 out:
1813 return status;
1814
1815 err_read_i2c_eeprom:
1816 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1817 hw->phy.id = 0;
1818 hw->phy.type = ixgbe_phy_unknown;
1819
1820 return IXGBE_ERR_SFP_NOT_PRESENT;
1821 }
1822
1823 /**
1824 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1825 * @hw: pointer to hardware structure
1826 * @list_offset: offset to the SFP ID list
1827 * @data_offset: offset to the SFP data block
1828 *
1829 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1830 * so it returns the offsets to the phy init sequence block.
1831 **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,u16 * list_offset,u16 * data_offset)1832 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1833 u16 *list_offset,
1834 u16 *data_offset)
1835 {
1836 u16 sfp_id;
1837 u16 sfp_type = hw->phy.sfp_type;
1838
1839 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1840
1841 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1842 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1843
1844 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1845 return IXGBE_ERR_SFP_NOT_PRESENT;
1846
1847 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1848 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1849 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1850
1851 /*
1852 * Limiting active cables and 1G Phys must be initialized as
1853 * SR modules
1854 */
1855 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1856 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1857 sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1858 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1859 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1860 sfp_type = ixgbe_sfp_type_srlr_core0;
1861 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1862 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1863 sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1864 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1865 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1866 sfp_type = ixgbe_sfp_type_srlr_core1;
1867
1868 /* Read offset to PHY init contents */
1869 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1870 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1871 "eeprom read at offset %d failed",
1872 IXGBE_PHY_INIT_OFFSET_NL);
1873 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1874 }
1875
1876 if ((!*list_offset) || (*list_offset == 0xFFFF))
1877 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1878
1879 /* Shift offset to first ID word */
1880 (*list_offset)++;
1881
1882 /*
1883 * Find the matching SFP ID in the EEPROM
1884 * and program the init sequence
1885 */
1886 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1887 goto err_phy;
1888
1889 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1890 if (sfp_id == sfp_type) {
1891 (*list_offset)++;
1892 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1893 goto err_phy;
1894 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1895 DEBUGOUT("SFP+ module not supported\n");
1896 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1897 } else {
1898 break;
1899 }
1900 } else {
1901 (*list_offset) += 2;
1902 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1903 goto err_phy;
1904 }
1905 }
1906
1907 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1908 DEBUGOUT("No matching SFP+ module found\n");
1909 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1910 }
1911
1912 return IXGBE_SUCCESS;
1913
1914 err_phy:
1915 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1916 "eeprom read at offset %d failed", *list_offset);
1917 return IXGBE_ERR_PHY;
1918 }
1919
1920 /**
1921 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1922 * @hw: pointer to hardware structure
1923 * @byte_offset: EEPROM byte offset to read
1924 * @eeprom_data: value read
1925 *
1926 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1927 **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1928 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1929 u8 *eeprom_data)
1930 {
1931 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1932
1933 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1934 IXGBE_I2C_EEPROM_DEV_ADDR,
1935 eeprom_data);
1936 }
1937
1938 /**
1939 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1940 * @hw: pointer to hardware structure
1941 * @byte_offset: byte offset at address 0xA2
1942 * @sff8472_data: value read
1943 *
1944 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1945 **/
ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1946 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1947 u8 *sff8472_data)
1948 {
1949 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1950 IXGBE_I2C_EEPROM_DEV_ADDR2,
1951 sff8472_data);
1952 }
1953
1954 /**
1955 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1956 * @hw: pointer to hardware structure
1957 * @byte_offset: EEPROM byte offset to write
1958 * @eeprom_data: value to write
1959 *
1960 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1961 **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1962 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1963 u8 eeprom_data)
1964 {
1965 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1966
1967 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1968 IXGBE_I2C_EEPROM_DEV_ADDR,
1969 eeprom_data);
1970 }
1971
1972 /**
1973 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1974 * @hw: pointer to hardware structure
1975 * @offset: eeprom offset to be read
1976 * @addr: I2C address to be read
1977 */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,u8 offset,u8 addr)1978 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1979 {
1980 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1981 offset == IXGBE_SFF_IDENTIFIER &&
1982 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1983 return true;
1984 return false;
1985 }
1986
1987 /**
1988 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1989 * @hw: pointer to hardware structure
1990 * @byte_offset: byte offset to read
1991 * @dev_addr: address to read from
1992 * @data: value read
1993 * @lock: true if to take and release semaphore
1994 *
1995 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1996 * a specified device address.
1997 **/
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data,bool lock)1998 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1999 u8 dev_addr, u8 *data, bool lock)
2000 {
2001 s32 status;
2002 u32 max_retry = 10;
2003 u32 retry = 0;
2004 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2005 bool nack = 1;
2006 *data = 0;
2007
2008 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2009
2010 if (hw->mac.type >= ixgbe_mac_X550)
2011 max_retry = 3;
2012 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2013 max_retry = IXGBE_SFP_DETECT_RETRIES;
2014
2015 do {
2016 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2017 return IXGBE_ERR_SWFW_SYNC;
2018
2019 ixgbe_i2c_start(hw);
2020
2021 /* Device Address and write indication */
2022 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2023 if (status != IXGBE_SUCCESS)
2024 goto fail;
2025
2026 status = ixgbe_get_i2c_ack(hw);
2027 if (status != IXGBE_SUCCESS)
2028 goto fail;
2029
2030 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2031 if (status != IXGBE_SUCCESS)
2032 goto fail;
2033
2034 status = ixgbe_get_i2c_ack(hw);
2035 if (status != IXGBE_SUCCESS)
2036 goto fail;
2037
2038 ixgbe_i2c_start(hw);
2039
2040 /* Device Address and read indication */
2041 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2042 if (status != IXGBE_SUCCESS)
2043 goto fail;
2044
2045 status = ixgbe_get_i2c_ack(hw);
2046 if (status != IXGBE_SUCCESS)
2047 goto fail;
2048
2049 ixgbe_clock_in_i2c_byte(hw, data);
2050
2051 status = ixgbe_clock_out_i2c_bit(hw, nack);
2052 if (status != IXGBE_SUCCESS)
2053 goto fail;
2054
2055 ixgbe_i2c_stop(hw);
2056 if (lock)
2057 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2058 return IXGBE_SUCCESS;
2059
2060 fail:
2061 ixgbe_i2c_bus_clear(hw);
2062 if (lock) {
2063 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2064 msec_delay(100);
2065 }
2066 if (retry < max_retry)
2067 DEBUGOUT("I2C byte read error - Retrying.\n");
2068 else
2069 DEBUGOUT("I2C byte read error.\n");
2070 retry++;
2071 } while (retry <= max_retry);
2072
2073 return status;
2074 }
2075
2076 /**
2077 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2078 * @hw: pointer to hardware structure
2079 * @byte_offset: byte offset to read
2080 * @dev_addr: address to read from
2081 * @data: value read
2082 *
2083 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2084 * a specified device address.
2085 **/
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2086 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2087 u8 dev_addr, u8 *data)
2088 {
2089 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2090 data, true);
2091 }
2092
2093 /**
2094 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2095 * @hw: pointer to hardware structure
2096 * @byte_offset: byte offset to read
2097 * @dev_addr: address to read from
2098 * @data: value read
2099 *
2100 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2101 * a specified device address.
2102 **/
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2103 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2104 u8 dev_addr, u8 *data)
2105 {
2106 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2107 data, false);
2108 }
2109
2110 /**
2111 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2112 * @hw: pointer to hardware structure
2113 * @byte_offset: byte offset to write
2114 * @dev_addr: address to write to
2115 * @data: value to write
2116 * @lock: true if to take and release semaphore
2117 *
2118 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2119 * a specified device address.
2120 **/
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data,bool lock)2121 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2122 u8 dev_addr, u8 data, bool lock)
2123 {
2124 s32 status;
2125 u32 max_retry = 1;
2126 u32 retry = 0;
2127 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2128
2129 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2130
2131 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2132 IXGBE_SUCCESS)
2133 return IXGBE_ERR_SWFW_SYNC;
2134
2135 do {
2136 ixgbe_i2c_start(hw);
2137
2138 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2139 if (status != IXGBE_SUCCESS)
2140 goto fail;
2141
2142 status = ixgbe_get_i2c_ack(hw);
2143 if (status != IXGBE_SUCCESS)
2144 goto fail;
2145
2146 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2147 if (status != IXGBE_SUCCESS)
2148 goto fail;
2149
2150 status = ixgbe_get_i2c_ack(hw);
2151 if (status != IXGBE_SUCCESS)
2152 goto fail;
2153
2154 status = ixgbe_clock_out_i2c_byte(hw, data);
2155 if (status != IXGBE_SUCCESS)
2156 goto fail;
2157
2158 status = ixgbe_get_i2c_ack(hw);
2159 if (status != IXGBE_SUCCESS)
2160 goto fail;
2161
2162 ixgbe_i2c_stop(hw);
2163 if (lock)
2164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2165 return IXGBE_SUCCESS;
2166
2167 fail:
2168 ixgbe_i2c_bus_clear(hw);
2169 if (retry < max_retry)
2170 DEBUGOUT("I2C byte write error - Retrying.\n");
2171 else
2172 DEBUGOUT("I2C byte write error.\n");
2173 retry++;
2174 } while (retry <= max_retry);
2175
2176 if (lock)
2177 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2178
2179 return status;
2180 }
2181
2182 /**
2183 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2184 * @hw: pointer to hardware structure
2185 * @byte_offset: byte offset to write
2186 * @dev_addr: address to write to
2187 * @data: value to write
2188 *
2189 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2190 * a specified device address.
2191 **/
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2192 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2193 u8 dev_addr, u8 data)
2194 {
2195 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2196 data, true);
2197 }
2198
2199 /**
2200 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2201 * @hw: pointer to hardware structure
2202 * @byte_offset: byte offset to write
2203 * @dev_addr: address to write to
2204 * @data: value to write
2205 *
2206 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2207 * a specified device address.
2208 **/
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2209 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2210 u8 dev_addr, u8 data)
2211 {
2212 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2213 data, false);
2214 }
2215
2216 /**
2217 * ixgbe_i2c_start - Sets I2C start condition
2218 * @hw: pointer to hardware structure
2219 *
2220 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2221 * Set bit-bang mode on X550 hardware.
2222 **/
ixgbe_i2c_start(struct ixgbe_hw * hw)2223 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2224 {
2225 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2226
2227 DEBUGFUNC("ixgbe_i2c_start");
2228
2229 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2230
2231 /* Start condition must begin with data and clock high */
2232 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2233 ixgbe_raise_i2c_clk(hw, &i2cctl);
2234
2235 /* Setup time for start condition (4.7us) */
2236 usec_delay(IXGBE_I2C_T_SU_STA);
2237
2238 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2239
2240 /* Hold time for start condition (4us) */
2241 usec_delay(IXGBE_I2C_T_HD_STA);
2242
2243 ixgbe_lower_i2c_clk(hw, &i2cctl);
2244
2245 /* Minimum low period of clock is 4.7 us */
2246 usec_delay(IXGBE_I2C_T_LOW);
2247
2248 }
2249
2250 /**
2251 * ixgbe_i2c_stop - Sets I2C stop condition
2252 * @hw: pointer to hardware structure
2253 *
2254 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2255 * Disables bit-bang mode and negates data output enable on X550
2256 * hardware.
2257 **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2258 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2259 {
2260 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2261 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2262 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2263 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2264
2265 DEBUGFUNC("ixgbe_i2c_stop");
2266
2267 /* Stop condition must begin with data low and clock high */
2268 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2269 ixgbe_raise_i2c_clk(hw, &i2cctl);
2270
2271 /* Setup time for stop condition (4us) */
2272 usec_delay(IXGBE_I2C_T_SU_STO);
2273
2274 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2275
2276 /* bus free time between stop and start (4.7us)*/
2277 usec_delay(IXGBE_I2C_T_BUF);
2278
2279 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2280 i2cctl &= ~bb_en_bit;
2281 i2cctl |= data_oe_bit | clk_oe_bit;
2282 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2283 IXGBE_WRITE_FLUSH(hw);
2284 }
2285 }
2286
2287 /**
2288 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2289 * @hw: pointer to hardware structure
2290 * @data: data byte to clock in
2291 *
2292 * Clocks in one byte data via I2C data/clock
2293 **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,u8 * data)2294 STATIC void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2295 {
2296 s32 i;
2297 bool bit = 0;
2298
2299 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2300
2301 *data = 0;
2302 for (i = 7; i >= 0; i--) {
2303 ixgbe_clock_in_i2c_bit(hw, &bit);
2304 *data |= bit << i;
2305 }
2306 }
2307
2308 /**
2309 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2310 * @hw: pointer to hardware structure
2311 * @data: data byte clocked out
2312 *
2313 * Clocks out one byte data via I2C data/clock
2314 **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,u8 data)2315 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2316 {
2317 s32 status = IXGBE_SUCCESS;
2318 s32 i;
2319 u32 i2cctl;
2320 bool bit;
2321
2322 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2323
2324 for (i = 7; i >= 0; i--) {
2325 bit = (data >> i) & 0x1;
2326 status = ixgbe_clock_out_i2c_bit(hw, bit);
2327
2328 if (status != IXGBE_SUCCESS)
2329 break;
2330 }
2331
2332 /* Release SDA line (set high) */
2333 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2334 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2335 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2336 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2337 IXGBE_WRITE_FLUSH(hw);
2338
2339 return status;
2340 }
2341
2342 /**
2343 * ixgbe_get_i2c_ack - Polls for I2C ACK
2344 * @hw: pointer to hardware structure
2345 *
2346 * Clocks in/out one bit via I2C data/clock
2347 **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2348 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2349 {
2350 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2351 s32 status = IXGBE_SUCCESS;
2352 u32 i = 0;
2353 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2354 u32 timeout = 10;
2355 bool ack = 1;
2356
2357 DEBUGFUNC("ixgbe_get_i2c_ack");
2358
2359 if (data_oe_bit) {
2360 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2361 i2cctl |= data_oe_bit;
2362 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2363 IXGBE_WRITE_FLUSH(hw);
2364 }
2365 ixgbe_raise_i2c_clk(hw, &i2cctl);
2366
2367 /* Minimum high period of clock is 4us */
2368 usec_delay(IXGBE_I2C_T_HIGH);
2369
2370 /* Poll for ACK. Note that ACK in I2C spec is
2371 * transition from 1 to 0 */
2372 for (i = 0; i < timeout; i++) {
2373 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2374 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2375
2376 usec_delay(1);
2377 if (!ack)
2378 break;
2379 }
2380
2381 if (ack) {
2382 DEBUGOUT("I2C ack was not received.\n");
2383 status = IXGBE_ERR_I2C;
2384 }
2385
2386 ixgbe_lower_i2c_clk(hw, &i2cctl);
2387
2388 /* Minimum low period of clock is 4.7 us */
2389 usec_delay(IXGBE_I2C_T_LOW);
2390
2391 return status;
2392 }
2393
2394 /**
2395 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2396 * @hw: pointer to hardware structure
2397 * @data: read data value
2398 *
2399 * Clocks in one bit via I2C data/clock
2400 **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2401 STATIC void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2402 {
2403 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2404 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2405
2406 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2407
2408 if (data_oe_bit) {
2409 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2410 i2cctl |= data_oe_bit;
2411 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2412 IXGBE_WRITE_FLUSH(hw);
2413 }
2414 ixgbe_raise_i2c_clk(hw, &i2cctl);
2415
2416 /* Minimum high period of clock is 4us */
2417 usec_delay(IXGBE_I2C_T_HIGH);
2418
2419 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2420 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2421
2422 ixgbe_lower_i2c_clk(hw, &i2cctl);
2423
2424 /* Minimum low period of clock is 4.7 us */
2425 usec_delay(IXGBE_I2C_T_LOW);
2426 }
2427
2428 /**
2429 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2430 * @hw: pointer to hardware structure
2431 * @data: data value to write
2432 *
2433 * Clocks out one bit via I2C data/clock
2434 **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2435 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2436 {
2437 s32 status;
2438 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2439
2440 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2441
2442 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2443 if (status == IXGBE_SUCCESS) {
2444 ixgbe_raise_i2c_clk(hw, &i2cctl);
2445
2446 /* Minimum high period of clock is 4us */
2447 usec_delay(IXGBE_I2C_T_HIGH);
2448
2449 ixgbe_lower_i2c_clk(hw, &i2cctl);
2450
2451 /* Minimum low period of clock is 4.7 us.
2452 * This also takes care of the data hold time.
2453 */
2454 usec_delay(IXGBE_I2C_T_LOW);
2455 } else {
2456 status = IXGBE_ERR_I2C;
2457 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2458 "I2C data was not set to %X\n", data);
2459 }
2460
2461 return status;
2462 }
2463
2464 /**
2465 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2466 * @hw: pointer to hardware structure
2467 * @i2cctl: Current value of I2CCTL register
2468 *
2469 * Raises the I2C clock line '0'->'1'
2470 * Negates the I2C clock output enable on X550 hardware.
2471 **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2472 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2473 {
2474 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2475 u32 i = 0;
2476 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2477 u32 i2cctl_r = 0;
2478
2479 DEBUGFUNC("ixgbe_raise_i2c_clk");
2480
2481 if (clk_oe_bit) {
2482 *i2cctl |= clk_oe_bit;
2483 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2484 }
2485
2486 for (i = 0; i < timeout; i++) {
2487 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2488
2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2490 IXGBE_WRITE_FLUSH(hw);
2491 /* SCL rise time (1000ns) */
2492 usec_delay(IXGBE_I2C_T_RISE);
2493
2494 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2495 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2496 break;
2497 }
2498 }
2499
2500 /**
2501 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2502 * @hw: pointer to hardware structure
2503 * @i2cctl: Current value of I2CCTL register
2504 *
2505 * Lowers the I2C clock line '1'->'0'
2506 * Asserts the I2C clock output enable on X550 hardware.
2507 **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2508 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2509 {
2510 DEBUGFUNC("ixgbe_lower_i2c_clk");
2511
2512 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2513 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2514
2515 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2516 IXGBE_WRITE_FLUSH(hw);
2517
2518 /* SCL fall time (300ns) */
2519 usec_delay(IXGBE_I2C_T_FALL);
2520 }
2521
2522 /**
2523 * ixgbe_set_i2c_data - Sets the I2C data bit
2524 * @hw: pointer to hardware structure
2525 * @i2cctl: Current value of I2CCTL register
2526 * @data: I2C data value (0 or 1) to set
2527 *
2528 * Sets the I2C data bit
2529 * Asserts the I2C data output enable on X550 hardware.
2530 **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl,bool data)2531 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2532 {
2533 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2534 s32 status = IXGBE_SUCCESS;
2535
2536 DEBUGFUNC("ixgbe_set_i2c_data");
2537
2538 if (data)
2539 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2540 else
2541 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2542 *i2cctl &= ~data_oe_bit;
2543
2544 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2545 IXGBE_WRITE_FLUSH(hw);
2546
2547 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2548 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2549
2550 if (!data) /* Can't verify data in this case */
2551 return IXGBE_SUCCESS;
2552 if (data_oe_bit) {
2553 *i2cctl |= data_oe_bit;
2554 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2555 IXGBE_WRITE_FLUSH(hw);
2556 }
2557
2558 /* Verify data was set correctly */
2559 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2560 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2561 status = IXGBE_ERR_I2C;
2562 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2563 "Error - I2C data was not set to %X.\n",
2564 data);
2565 }
2566
2567 return status;
2568 }
2569
2570 /**
2571 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2572 * @hw: pointer to hardware structure
2573 * @i2cctl: Current value of I2CCTL register
2574 *
2575 * Returns the I2C data bit value
2576 * Negates the I2C data output enable on X550 hardware.
2577 **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl)2578 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2579 {
2580 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2581 bool data;
2582
2583 DEBUGFUNC("ixgbe_get_i2c_data");
2584
2585 if (data_oe_bit) {
2586 *i2cctl |= data_oe_bit;
2587 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2588 IXGBE_WRITE_FLUSH(hw);
2589 usec_delay(IXGBE_I2C_T_FALL);
2590 }
2591
2592 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2593 data = 1;
2594 else
2595 data = 0;
2596
2597 return data;
2598 }
2599
2600 /**
2601 * ixgbe_i2c_bus_clear - Clears the I2C bus
2602 * @hw: pointer to hardware structure
2603 *
2604 * Clears the I2C bus by sending nine clock pulses.
2605 * Used when data line is stuck low.
2606 **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2607 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2608 {
2609 u32 i2cctl;
2610 u32 i;
2611
2612 DEBUGFUNC("ixgbe_i2c_bus_clear");
2613
2614 ixgbe_i2c_start(hw);
2615 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2616
2617 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2618
2619 for (i = 0; i < 9; i++) {
2620 ixgbe_raise_i2c_clk(hw, &i2cctl);
2621
2622 /* Min high period of clock is 4us */
2623 usec_delay(IXGBE_I2C_T_HIGH);
2624
2625 ixgbe_lower_i2c_clk(hw, &i2cctl);
2626
2627 /* Min low period of clock is 4.7us*/
2628 usec_delay(IXGBE_I2C_T_LOW);
2629 }
2630
2631 ixgbe_i2c_start(hw);
2632
2633 /* Put the i2c bus back to default state */
2634 ixgbe_i2c_stop(hw);
2635 }
2636
2637 /**
2638 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2639 * @hw: pointer to hardware structure
2640 *
2641 * Checks if the LASI temp alarm status was triggered due to overtemp
2642 **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2643 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2644 {
2645 s32 status = IXGBE_SUCCESS;
2646 u16 phy_data = 0;
2647
2648 DEBUGFUNC("ixgbe_tn_check_overtemp");
2649
2650 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2651 goto out;
2652
2653 /* Check that the LASI temp alarm status was triggered */
2654 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2655 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2656
2657 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2658 goto out;
2659
2660 status = IXGBE_ERR_OVERTEMP;
2661 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2662 out:
2663 return status;
2664 }
2665
2666 /**
2667 * ixgbe_set_copper_phy_power - Control power for copper phy
2668 * @hw: pointer to hardware structure
2669 * @on: true for on, false for off
2670 */
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2671 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2672 {
2673 u32 status;
2674 u16 reg;
2675
2676 if (!on && ixgbe_mng_present(hw))
2677 return 0;
2678
2679 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2680 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2681 ®);
2682 if (status)
2683 return status;
2684
2685 if (on) {
2686 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2687 } else {
2688 if (ixgbe_check_reset_blocked(hw))
2689 return 0;
2690 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2691 }
2692
2693 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2694 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2695 reg);
2696 return status;
2697 }
2698