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Searched refs:regval (Results 1 – 25 of 30) sorted by relevance

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/dpdk/drivers/common/cnxk/
H A Droc_nix_tm_utils.c11 uint64_t regval; in nix_tm_shaper2regval() local
19 return regval; in nix_tm_shaper2regval()
27 return regval; in nix_tm_shaper2regval()
503 regval[k] = 0; in nix_tm_tl1_default_prep()
569 regval[k] = parent << 16; in nix_tm_topology_reg_prep()
576 regval[k] = parent << 16; in nix_tm_topology_reg_prep()
586 regval[k] = BIT_ULL(12); in nix_tm_topology_reg_prep()
593 regval[k] = parent << 16; in nix_tm_topology_reg_prep()
616 regval[k] = parent << 16; in nix_tm_topology_reg_prep()
699 regval[k] = rr_quantum; in nix_tm_sched_reg_prep()
[all …]
H A Droc_nix_tm_ops.c693 nix_tm_sw_xoff_prep(node, suspend, req->reg, req->regval); in roc_nix_tm_node_suspend_resume()
806 k = nix_tm_sw_xoff_prep(node, true, req->reg, req->regval); in roc_nix_tm_node_shaper_update()
880 req->reg, req->regval); in roc_nix_tm_node_parent_update()
894 &req->regval[k]); in roc_nix_tm_node_parent_update()
905 nix_tm_sched_reg_prep(nix, node, req->reg, req->regval); in roc_nix_tm_node_parent_update()
919 &req->regval[k]); in roc_nix_tm_node_parent_update()
930 req->reg, req->regval); in roc_nix_tm_node_parent_update()
976 volatile uint64_t *reg, *regval; in roc_nix_tm_rlimit_sq() local
999 regval = req->regval; in roc_nix_tm_rlimit_sq()
1002 k += nix_tm_sw_xoff_prep(parent, true, &reg[k], &regval[k]); in roc_nix_tm_rlimit_sq()
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H A Droc_nix_tm.c37 uint64_t regval[MAX_REGS_PER_MBOX_MSG]; in nix_tm_node_reg_conf() local
46 memset(regval, 0, sizeof(regval)); in nix_tm_node_reg_conf()
59 req->regval); in nix_tm_node_reg_conf()
70 k += nix_tm_sched_reg_prep(nix, node, &reg[k], &regval[k]); in nix_tm_node_reg_conf()
84 mbox_memcpy(req->regval, regval, sizeof(uint64_t) * k); in nix_tm_node_reg_conf()
306 req->regval); in nix_tm_clear_path_xoff()
373 req->regval[k] = enable ? tc : 0; in nix_tm_bp_config_set()
374 req->regval[k] |= enable ? BIT_ULL(13) : 0; in nix_tm_bp_config_set()
447 enable &= !!(rsp->regval[i] & BIT_ULL(13)); in nix_tm_bp_config_get()
458 enable &= !!(rsp->regval[i] & BIT_ULL(13)); in nix_tm_bp_config_get()
[all …]
H A Droc_nix_priv.h421 volatile uint64_t *reg, volatile uint64_t *regval);
437 volatile uint64_t *regval);
440 volatile uint64_t *regval,
444 volatile uint64_t *regval);
448 volatile uint64_t *regval);
H A Droc_nix_tm_mark.c42 volatile uint64_t *regval, in prepare_tm_shaper_red_algo() argument
53 regval[k] = ((uint64_t)tm_node->red_algo << 9); in prepare_tm_shaper_red_algo()
117 k = prepare_tm_shaper_red_algo(tm_node, req->reg, req->regval, in nix_tm_update_red_algo()
H A Droc_nix_debug.c1097 rsp->regval[j]); in nix_tm_dump_lvl()
1122 rsp->regval[j]); in nix_tm_dump_lvl()
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_82598.c226 u32 regval; in ixgbe_start_hw_82598() local
239 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); in ixgbe_start_hw_82598()
240 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_start_hw_82598()
241 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); in ixgbe_start_hw_82598()
246 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_82598()
247 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_start_hw_82598()
249 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_82598()
1334 u32 regval; in ixgbe_enable_relaxed_ordering_82598() local
1343 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_enable_relaxed_ordering_82598()
1350 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_enable_relaxed_ordering_82598()
[all …]
H A Dixgbe_82598.h23 s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval);
H A Dixgbe_82599.h32 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
H A Dixgbe_common.c423 u32 regval; in ixgbe_start_hw_gen2() local
435 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_start_hw_gen2()
440 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_gen2()
441 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_start_hw_gen2()
443 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_gen2()
3409 if (regval & IXGBE_RXCTRL_RXEN) in ixgbe_enable_rx_dma_generic()
4411 u32 regval; in ixgbe_enable_relaxed_ordering_gen2() local
4419 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_enable_relaxed_ordering_gen2()
4424 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_enable_relaxed_ordering_gen2()
4425 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_enable_relaxed_ordering_gen2()
[all …]
H A Dixgbe_common.h79 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
H A Dixgbe_api.c1591 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma() argument
1594 (hw, regval), IXGBE_NOT_IMPLEMENTED); in ixgbe_enable_rx_dma()
H A Dixgbe_api.h118 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
/dpdk/drivers/net/bnxt/tf_ulp/
H A Dulp_mapper.c70 uint64_t *regval, in ulp_mapper_glb_resource_read() argument
122 uint64_t regval; in ulp_mapper_resource_ident_allocate() local
174 uint64_t regval; in ulp_mapper_resource_index_tbl_alloc() local
2606 regval = index; in ulp_mapper_index_tbl_process()
2607 regval = tfp_cpu_to_be_64(regval); in ulp_mapper_index_tbl_process()
3113 uint64_t regval; in ulp_mapper_app_glb_resource_info_init() local
3225 uint64_t regval; in ulp_mapper_cond_opc_process() local
3373 uint64_t regval; in ulp_mapper_func_opr_compute() local
3586 uint64_t regval; in ulp_mapper_conflict_resolution_process() local
3606 if (regval) { in ulp_mapper_conflict_resolution_process()
[all …]
/dpdk/drivers/net/e1000/base/
H A De1000_ich8lan.c133 u16 regval; member
146 u16 regval; member
157 u16 regval; member
3632 hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
3659 hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
4386 hsflctl.regval = in e1000_write_flash_data_ich8lan()
4389 hsflctl.regval = in e1000_write_flash_data_ich8lan()
4404 hsflctl.regval); in e1000_write_flash_data_ich8lan()
4497 hsflctl.regval); in e1000_write_flash_data32_ich8lan()
4695 hsflctl.regval = in e1000_erase_flash_bank_ich8lan()
[all …]
/dpdk/drivers/net/ice/base/
H A Dice_nvm.h66 u32 regval; /* Storage for register value */ member
H A Dice_nvm.c1197 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval)) in ice_validate_nvm_rw_reg()
1257 data->regval = rd32(hw, cmd->offset); in ice_nvm_access_read()
1293 cmd->offset, data->regval); in ice_nvm_access_write()
1296 wr32(hw, cmd->offset, data->regval); in ice_nvm_access_write()
H A Dice_ptp_hw.c992 u32 regval; in ice_ptp_init_phc_e822() local
997 regval = rd32(hw, PF_SB_REM_DEV_CTL); in ice_ptp_init_phc_e822()
998 regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | in ice_ptp_init_phc_e822()
1000 wr32(hw, PF_SB_REM_DEV_CTL, regval); in ice_ptp_init_phc_e822()
/dpdk/drivers/net/e1000/
H A Digb_ethdev.c2764 uint32_t mask, regval; in eth_igb_rxq_interrupt_setup() local
2779 regval = E1000_READ_REG(hw, E1000_EIMS); in eth_igb_rxq_interrupt_setup()
2780 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); in eth_igb_rxq_interrupt_setup()
5135 uint32_t regval; in eth_igb_rx_queue_intr_enable() local
5137 regval = E1000_READ_REG(hw, E1000_EIMS); in eth_igb_rx_queue_intr_enable()
5199 uint32_t tmpval, regval, intr_mask; in eth_igb_configure_msix_intr() local
5233 regval = E1000_READ_REG(hw, E1000_EIAC); in eth_igb_configure_msix_intr()
5235 regval = E1000_READ_REG(hw, E1000_EIAM); in eth_igb_configure_msix_intr()
5256 regval = E1000_READ_REG(hw, E1000_EIAC); in eth_igb_configure_msix_intr()
5260 regval = E1000_READ_REG(hw, E1000_EIMS); in eth_igb_configure_msix_intr()
[all …]
H A Dem_ethdev.c1454 uint32_t regval; in eth_em_interrupt_setup() local
1460 regval = E1000_READ_REG(hw, E1000_IMS); in eth_em_interrupt_setup()
1462 regval | E1000_ICR_LSC | E1000_ICR_OTHER); in eth_em_interrupt_setup()
/dpdk/drivers/net/ngbe/base/
H A Dngbe_hw.h83 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval);
H A Dngbe_type.h270 s32 (*enable_rx_dma)(struct ngbe_hw *hw, u32 regval);
H A Dngbe_hw.c1788 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval) in ngbe_enable_rx_dma() argument
1798 if (regval & NGBE_PBRXCTL_ENA) in ngbe_enable_rx_dma()
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_hw.h109 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval);
/dpdk/drivers/net/ice/
H A Dice_rxtx.c278 uint32_t regval; in ice_program_hw_rx_queue() local
354 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) & in ice_program_hw_rx_queue()
361 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) & in ice_program_hw_rx_queue()
365 regval |= QRXFLXP_CNTXT_TS_M; in ice_program_hw_rx_queue()
367 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval); in ice_program_hw_rx_queue()
734 uint32_t regval; in ice_fdir_program_hw_rx_queue() local
766 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) & in ice_fdir_program_hw_rx_queue()
773 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) & in ice_fdir_program_hw_rx_queue()
776 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval); in ice_fdir_program_hw_rx_queue()

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