1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #include "roc_api.h"
6 #include "roc_priv.h"
7
8 #define nix_dump plt_dump
9 #define NIX_REG_INFO(reg) \
10 { \
11 reg, #reg \
12 }
13 #define NIX_REG_NAME_SZ 48
14
15 #define nix_dump_no_nl plt_dump_no_nl
16
17 struct nix_lf_reg_info {
18 uint32_t offset;
19 const char *name;
20 };
21
22 static const struct nix_lf_reg_info nix_lf_reg[] = {
23 NIX_REG_INFO(NIX_LF_RX_SECRETX(0)),
24 NIX_REG_INFO(NIX_LF_RX_SECRETX(1)),
25 NIX_REG_INFO(NIX_LF_RX_SECRETX(2)),
26 NIX_REG_INFO(NIX_LF_RX_SECRETX(3)),
27 NIX_REG_INFO(NIX_LF_RX_SECRETX(4)),
28 NIX_REG_INFO(NIX_LF_RX_SECRETX(5)),
29 NIX_REG_INFO(NIX_LF_CFG),
30 NIX_REG_INFO(NIX_LF_GINT),
31 NIX_REG_INFO(NIX_LF_GINT_W1S),
32 NIX_REG_INFO(NIX_LF_GINT_ENA_W1C),
33 NIX_REG_INFO(NIX_LF_GINT_ENA_W1S),
34 NIX_REG_INFO(NIX_LF_ERR_INT),
35 NIX_REG_INFO(NIX_LF_ERR_INT_W1S),
36 NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C),
37 NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S),
38 NIX_REG_INFO(NIX_LF_RAS),
39 NIX_REG_INFO(NIX_LF_RAS_W1S),
40 NIX_REG_INFO(NIX_LF_RAS_ENA_W1C),
41 NIX_REG_INFO(NIX_LF_RAS_ENA_W1S),
42 NIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG),
43 NIX_REG_INFO(NIX_LF_MNQ_ERR_DBG),
44 NIX_REG_INFO(NIX_LF_SEND_ERR_DBG),
45 };
46
47 static void
nix_bitmap_dump(struct plt_bitmap * bmp)48 nix_bitmap_dump(struct plt_bitmap *bmp)
49 {
50 uint32_t pos = 0, start_pos;
51 uint64_t slab = 0;
52 int i;
53
54 plt_bitmap_scan_init(bmp);
55 if (!plt_bitmap_scan(bmp, &pos, &slab))
56 return;
57
58 start_pos = pos;
59
60 nix_dump_no_nl(" \t\t[");
61 do {
62 if (!slab)
63 break;
64 i = 0;
65
66 for (i = 0; i < 64; i++)
67 if (slab & (1ULL << i))
68 nix_dump_no_nl("%d, ", i);
69
70 if (!plt_bitmap_scan(bmp, &pos, &slab))
71 break;
72 } while (start_pos != pos);
73 nix_dump_no_nl(" ]");
74 }
75
76 int
roc_nix_lf_get_reg_count(struct roc_nix * roc_nix)77 roc_nix_lf_get_reg_count(struct roc_nix *roc_nix)
78 {
79 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
80 int reg_count;
81
82 if (roc_nix == NULL)
83 return NIX_ERR_PARAM;
84
85 reg_count = PLT_DIM(nix_lf_reg);
86 /* NIX_LF_TX_STATX */
87 reg_count += nix->lf_tx_stats;
88 /* NIX_LF_RX_STATX */
89 reg_count += nix->lf_rx_stats;
90 /* NIX_LF_QINTX_CNT*/
91 reg_count += nix->qints;
92 /* NIX_LF_QINTX_INT */
93 reg_count += nix->qints;
94 /* NIX_LF_QINTX_ENA_W1S */
95 reg_count += nix->qints;
96 /* NIX_LF_QINTX_ENA_W1C */
97 reg_count += nix->qints;
98 /* NIX_LF_CINTX_CNT */
99 reg_count += nix->cints;
100 /* NIX_LF_CINTX_WAIT */
101 reg_count += nix->cints;
102 /* NIX_LF_CINTX_INT */
103 reg_count += nix->cints;
104 /* NIX_LF_CINTX_INT_W1S */
105 reg_count += nix->cints;
106 /* NIX_LF_CINTX_ENA_W1S */
107 reg_count += nix->cints;
108 /* NIX_LF_CINTX_ENA_W1C */
109 reg_count += nix->cints;
110
111 return reg_count;
112 }
113
114 int
nix_lf_gen_reg_dump(uintptr_t nix_lf_base,uint64_t * data)115 nix_lf_gen_reg_dump(uintptr_t nix_lf_base, uint64_t *data)
116 {
117 bool dump_stdout;
118 uint64_t reg;
119 uint32_t i;
120
121 dump_stdout = data ? 0 : 1;
122
123 for (i = 0; i < PLT_DIM(nix_lf_reg); i++) {
124 reg = plt_read64(nix_lf_base + nix_lf_reg[i].offset);
125 if (dump_stdout && reg)
126 nix_dump("%32s = 0x%" PRIx64, nix_lf_reg[i].name, reg);
127 if (data)
128 *data++ = reg;
129 }
130
131 return i;
132 }
133
134 int
nix_lf_stat_reg_dump(uintptr_t nix_lf_base,uint64_t * data,uint8_t lf_tx_stats,uint8_t lf_rx_stats)135 nix_lf_stat_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint8_t lf_tx_stats,
136 uint8_t lf_rx_stats)
137 {
138 uint32_t i, count = 0;
139 bool dump_stdout;
140 uint64_t reg;
141
142 dump_stdout = data ? 0 : 1;
143
144 /* NIX_LF_TX_STATX */
145 for (i = 0; i < lf_tx_stats; i++) {
146 reg = plt_read64(nix_lf_base + NIX_LF_TX_STATX(i));
147 if (dump_stdout && reg)
148 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_TX_STATX", i,
149 reg);
150 if (data)
151 *data++ = reg;
152 }
153 count += i;
154
155 /* NIX_LF_RX_STATX */
156 for (i = 0; i < lf_rx_stats; i++) {
157 reg = plt_read64(nix_lf_base + NIX_LF_RX_STATX(i));
158 if (dump_stdout && reg)
159 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_RX_STATX", i,
160 reg);
161 if (data)
162 *data++ = reg;
163 }
164
165 return count + i;
166 }
167
168 int
nix_lf_int_reg_dump(uintptr_t nix_lf_base,uint64_t * data,uint16_t qints,uint16_t cints)169 nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints,
170 uint16_t cints)
171 {
172 uint32_t i, count = 0;
173 bool dump_stdout;
174 uint64_t reg;
175
176 dump_stdout = data ? 0 : 1;
177
178 /* NIX_LF_QINTX_CNT*/
179 for (i = 0; i < qints; i++) {
180 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));
181 if (dump_stdout && reg)
182 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_CNT", i,
183 reg);
184 if (data)
185 *data++ = reg;
186 }
187 count += i;
188
189 /* NIX_LF_QINTX_INT */
190 for (i = 0; i < qints; i++) {
191 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_INT(i));
192 if (dump_stdout && reg)
193 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_INT", i,
194 reg);
195 if (data)
196 *data++ = reg;
197 }
198 count += i;
199
200 /* NIX_LF_QINTX_ENA_W1S */
201 for (i = 0; i < qints; i++) {
202 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));
203 if (dump_stdout && reg)
204 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1S",
205 i, reg);
206 if (data)
207 *data++ = reg;
208 }
209 count += i;
210
211 /* NIX_LF_QINTX_ENA_W1C */
212 for (i = 0; i < qints; i++) {
213 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));
214 if (dump_stdout && reg)
215 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1C",
216 i, reg);
217 if (data)
218 *data++ = reg;
219 }
220 count += i;
221
222 /* NIX_LF_CINTX_CNT */
223 for (i = 0; i < cints; i++) {
224 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));
225 if (dump_stdout && reg)
226 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_CNT", i,
227 reg);
228 if (data)
229 *data++ = reg;
230 }
231 count += i;
232
233 /* NIX_LF_CINTX_WAIT */
234 for (i = 0; i < cints; i++) {
235 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));
236 if (dump_stdout && reg)
237 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_WAIT", i,
238 reg);
239 if (data)
240 *data++ = reg;
241 }
242 count += i;
243
244 /* NIX_LF_CINTX_INT */
245 for (i = 0; i < cints; i++) {
246 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT(i));
247 if (dump_stdout && reg)
248 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT", i,
249 reg);
250 if (data)
251 *data++ = reg;
252 }
253 count += i;
254
255 /* NIX_LF_CINTX_INT_W1S */
256 for (i = 0; i < cints; i++) {
257 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));
258 if (dump_stdout && reg)
259 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT_W1S",
260 i, reg);
261 if (data)
262 *data++ = reg;
263 }
264 count += i;
265
266 /* NIX_LF_CINTX_ENA_W1S */
267 for (i = 0; i < cints; i++) {
268 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));
269 if (dump_stdout && reg)
270 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1S",
271 i, reg);
272 if (data)
273 *data++ = reg;
274 }
275 count += i;
276
277 /* NIX_LF_CINTX_ENA_W1C */
278 for (i = 0; i < cints; i++) {
279 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));
280 if (dump_stdout && reg)
281 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1C",
282 i, reg);
283 if (data)
284 *data++ = reg;
285 }
286
287 return count + i;
288 }
289
290 int
roc_nix_lf_reg_dump(struct roc_nix * roc_nix,uint64_t * data)291 roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)
292 {
293 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
294 bool dump_stdout = data ? 0 : 1;
295 uintptr_t nix_base;
296 uint32_t i;
297
298 if (roc_nix == NULL)
299 return NIX_ERR_PARAM;
300
301 nix_base = nix->base;
302 /* General registers */
303 i = nix_lf_gen_reg_dump(nix_base, data);
304
305 /* Rx, Tx stat registers */
306 i += nix_lf_stat_reg_dump(nix_base, dump_stdout ? NULL : &data[i],
307 nix->lf_tx_stats, nix->lf_rx_stats);
308
309 /* Intr registers */
310 i += nix_lf_int_reg_dump(nix_base, dump_stdout ? NULL : &data[i],
311 nix->qints, nix->cints);
312
313 return 0;
314 }
315
316 int
nix_q_ctx_get(struct dev * dev,uint8_t ctype,uint16_t qid,__io void ** ctx_p)317 nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)
318 {
319 struct mbox *mbox = dev->mbox;
320 int rc;
321
322 if (roc_model_is_cn9k()) {
323 struct nix_aq_enq_rsp *rsp;
324 struct nix_aq_enq_req *aq;
325 int rc;
326
327 aq = mbox_alloc_msg_nix_aq_enq(mbox);
328 if (!aq)
329 return -ENOSPC;
330
331 aq->qidx = qid;
332 aq->ctype = ctype;
333 aq->op = NIX_AQ_INSTOP_READ;
334
335 rc = mbox_process_msg(mbox, (void *)&rsp);
336 if (rc)
337 return rc;
338 if (ctype == NIX_AQ_CTYPE_RQ)
339 *ctx_p = &rsp->rq;
340 else if (ctype == NIX_AQ_CTYPE_SQ)
341 *ctx_p = &rsp->sq;
342 else
343 *ctx_p = &rsp->cq;
344 } else {
345 struct nix_cn10k_aq_enq_rsp *rsp;
346 struct nix_cn10k_aq_enq_req *aq;
347
348 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
349 if (!aq)
350 return -ENOSPC;
351
352 aq->qidx = qid;
353 aq->ctype = ctype;
354 aq->op = NIX_AQ_INSTOP_READ;
355
356 rc = mbox_process_msg(mbox, (void *)&rsp);
357 if (rc)
358 return rc;
359
360 if (ctype == NIX_AQ_CTYPE_RQ)
361 *ctx_p = &rsp->rq;
362 else if (ctype == NIX_AQ_CTYPE_SQ)
363 *ctx_p = &rsp->sq;
364 else
365 *ctx_p = &rsp->cq;
366 }
367 return 0;
368 }
369
370 static inline void
nix_cn9k_lf_sq_dump(__io struct nix_sq_ctx_s * ctx,uint32_t * sqb_aura_p)371 nix_cn9k_lf_sq_dump(__io struct nix_sq_ctx_s *ctx, uint32_t *sqb_aura_p)
372 {
373 nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
374 ctx->sqe_way_mask, ctx->cq);
375 nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
376 ctx->sdp_mcast, ctx->substream);
377 nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx,
378 ctx->ena);
379
380 nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
381 ctx->sqb_count, ctx->default_chan);
382 nix_dump("W1: smq_rr_quantum \t\t%d\nW1: sso_ena \t\t\t%d",
383 ctx->smq_rr_quantum, ctx->sso_ena);
384 nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
385 ctx->xoff, ctx->cq_ena, ctx->smq);
386
387 nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
388 ctx->sqe_stype, ctx->sq_int_ena);
389 nix_dump("W2: sq_int \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int,
390 ctx->sqb_aura);
391 nix_dump("W2: smq_rr_count \t\t%d\n", ctx->smq_rr_count);
392
393 nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
394 ctx->smq_next_sq_vld, ctx->smq_pend);
395 nix_dump("W3: smenq_next_sqb_vld \t%d\nW3: head_offset\t\t\t%d",
396 ctx->smenq_next_sqb_vld, ctx->head_offset);
397 nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
398 ctx->smenq_offset, ctx->tail_offset);
399 nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
400 ctx->smq_lso_segnum, ctx->smq_next_sq);
401 nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis,
402 ctx->lmt_dis);
403 nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
404 ctx->cq_limit, ctx->max_sqe_size);
405
406 nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
407 nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
408 nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
409 nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
410 nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
411
412 nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
413 ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
414 nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
415 ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
416 nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
417 ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
418 nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
419
420 nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
421 (uint64_t)ctx->scm_lso_rem);
422 nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
423 nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
424 nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
425 (uint64_t)ctx->drop_octs);
426 nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
427 (uint64_t)ctx->drop_pkts);
428
429 *sqb_aura_p = ctx->sqb_aura;
430 }
431
432 static inline void
nix_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s * ctx,uint32_t * sqb_aura_p)433 nix_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p)
434 {
435 nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
436 ctx->sqe_way_mask, ctx->cq);
437 nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
438 ctx->sdp_mcast, ctx->substream);
439 nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx,
440 ctx->ena);
441
442 nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
443 ctx->sqb_count, ctx->default_chan);
444 nix_dump("W1: smq_rr_weight \t\t%d\nW1: sso_ena \t\t\t%d",
445 ctx->smq_rr_weight, ctx->sso_ena);
446 nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
447 ctx->xoff, ctx->cq_ena, ctx->smq);
448
449 nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
450 ctx->sqe_stype, ctx->sq_int_ena);
451 nix_dump("W2: sq_int \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int,
452 ctx->sqb_aura);
453 nix_dump("W2: smq_rr_count[ub:lb] \t\t%x:%x\n", ctx->smq_rr_count_ub,
454 ctx->smq_rr_count_lb);
455
456 nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
457 ctx->smq_next_sq_vld, ctx->smq_pend);
458 nix_dump("W3: smenq_next_sqb_vld \t%d\nW3: head_offset\t\t\t%d",
459 ctx->smenq_next_sqb_vld, ctx->head_offset);
460 nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
461 ctx->smenq_offset, ctx->tail_offset);
462 nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
463 ctx->smq_lso_segnum, ctx->smq_next_sq);
464 nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis,
465 ctx->lmt_dis);
466 nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
467 ctx->cq_limit, ctx->max_sqe_size);
468
469 nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
470 nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
471 nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
472 nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
473 nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
474
475 nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
476 ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
477 nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
478 ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
479 nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
480 ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
481 nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
482
483 nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
484 (uint64_t)ctx->scm_lso_rem);
485 nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
486 nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
487 nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
488 (uint64_t)ctx->drop_octs);
489 nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
490 (uint64_t)ctx->drop_pkts);
491
492 *sqb_aura_p = ctx->sqb_aura;
493 }
494
495 static inline void
nix_cn9k_lf_rq_dump(__io struct nix_rq_ctx_s * ctx)496 nix_cn9k_lf_rq_dump(__io struct nix_rq_ctx_s *ctx)
497 {
498 nix_dump("W0: wqe_aura \t\t\t%d\nW0: substream \t\t\t0x%03x",
499 ctx->wqe_aura, ctx->substream);
500 nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq,
501 ctx->ena_wqwd);
502 nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
503 ctx->ipsech_ena, ctx->sso_ena);
504 nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
505
506 nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
507 ctx->lpb_drop_ena, ctx->spb_drop_ena);
508 nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
509 ctx->xqe_drop_ena, ctx->wqe_caching);
510 nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
511 ctx->pb_caching, ctx->sso_tt);
512 nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp,
513 ctx->lpb_aura);
514 nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
515
516 nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
517 ctx->xqe_hdr_split, ctx->xqe_imm_copy);
518 nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
519 ctx->xqe_imm_size, ctx->later_skip);
520 nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
521 ctx->first_skip, ctx->lpb_sizem1);
522 nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena,
523 ctx->wqe_skip);
524 nix_dump("W2: spb_sizem1 \t\t\t%d\n", ctx->spb_sizem1);
525
526 nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
527 ctx->spb_pool_pass, ctx->spb_pool_drop);
528 nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
529 ctx->spb_aura_pass, ctx->spb_aura_drop);
530 nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
531 ctx->wqe_pool_pass, ctx->wqe_pool_drop);
532 nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
533 ctx->xqe_pass, ctx->xqe_drop);
534
535 nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
536 ctx->qint_idx, ctx->rq_int_ena);
537 nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int,
538 ctx->lpb_pool_pass);
539 nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
540 ctx->lpb_pool_drop, ctx->lpb_aura_pass);
541 nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
542
543 nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
544 ctx->flow_tagw, ctx->bad_utag);
545 nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag,
546 ctx->ltag);
547
548 nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
549 nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
550 nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
551 nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
552 nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
553 }
554
555 void
nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s * ctx)556 nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx)
557 {
558 nix_dump("W0: wqe_aura \t\t\t%d\nW0: len_ol3_dis \t\t\t%d",
559 ctx->wqe_aura, ctx->len_ol3_dis);
560 nix_dump("W0: len_ol4_dis \t\t\t%d\nW0: len_il3_dis \t\t\t%d",
561 ctx->len_ol4_dis, ctx->len_il3_dis);
562 nix_dump("W0: len_il4_dis \t\t\t%d\nW0: csum_ol4_dis \t\t\t%d",
563 ctx->len_il4_dis, ctx->csum_ol4_dis);
564 nix_dump("W0: csum_ol3_dis \t\t\t%d\nW0: lenerr_dis \t\t\t%d",
565 ctx->csum_ol4_dis, ctx->lenerr_dis);
566 nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq,
567 ctx->ena_wqwd);
568 nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
569 ctx->ipsech_ena, ctx->sso_ena);
570 nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
571
572 nix_dump("W1: chi_ena \t\t%d\nW1: ipsecd_drop_en \t\t%d", ctx->chi_ena,
573 ctx->ipsecd_drop_en);
574 nix_dump("W1: pb_stashing \t\t\t%d", ctx->pb_stashing);
575 nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
576 ctx->lpb_drop_ena, ctx->spb_drop_ena);
577 nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
578 ctx->xqe_drop_ena, ctx->wqe_caching);
579 nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
580 ctx->pb_caching, ctx->sso_tt);
581 nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp,
582 ctx->lpb_aura);
583 nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
584
585 nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
586 ctx->xqe_hdr_split, ctx->xqe_imm_copy);
587 nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
588 ctx->xqe_imm_size, ctx->later_skip);
589 nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
590 ctx->first_skip, ctx->lpb_sizem1);
591 nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena,
592 ctx->wqe_skip);
593 nix_dump("W2: spb_sizem1 \t\t\t%d\nW2: policer_ena \t\t\t%d",
594 ctx->spb_sizem1, ctx->policer_ena);
595 nix_dump("W2: band_prof_id \t\t\t%d", ctx->band_prof_id);
596
597 nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
598 ctx->spb_pool_pass, ctx->spb_pool_drop);
599 nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
600 ctx->spb_aura_pass, ctx->spb_aura_drop);
601 nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
602 ctx->wqe_pool_pass, ctx->wqe_pool_drop);
603 nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
604 ctx->xqe_pass, ctx->xqe_drop);
605
606 nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
607 ctx->qint_idx, ctx->rq_int_ena);
608 nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int,
609 ctx->lpb_pool_pass);
610 nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
611 ctx->lpb_pool_drop, ctx->lpb_aura_pass);
612 nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
613
614 nix_dump("W5: vwqe_skip \t\t\t%d\nW5: max_vsize_exp \t\t\t%d",
615 ctx->vwqe_skip, ctx->max_vsize_exp);
616 nix_dump("W5: vtime_wait \t\t\t%d\nW5: vwqe_ena \t\t\t%d",
617 ctx->vtime_wait, ctx->max_vsize_exp);
618 nix_dump("W5: ipsec_vwqe \t\t\t%d", ctx->ipsec_vwqe);
619 nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
620 ctx->flow_tagw, ctx->bad_utag);
621 nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag,
622 ctx->ltag);
623
624 nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
625 nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
626 nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
627 nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
628 nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
629 }
630
631 static inline void
nix_lf_cq_dump(__io struct nix_cq_ctx_s * ctx)632 nix_lf_cq_dump(__io struct nix_cq_ctx_s *ctx)
633 {
634 nix_dump("W0: base \t\t\t0x%" PRIx64 "\n", ctx->base);
635
636 nix_dump("W1: wrptr \t\t\t%" PRIx64 "", (uint64_t)ctx->wrptr);
637 nix_dump("W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d", ctx->avg_con,
638 ctx->cint_idx);
639 nix_dump("W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d", ctx->cq_err,
640 ctx->qint_idx);
641 nix_dump("W1: bpid \t\t\t%d\nW1: bp_ena \t\t\t%d\n", ctx->bpid,
642 ctx->bp_ena);
643
644 nix_dump("W2: update_time \t\t%d\nW2: avg_level \t\t\t%d",
645 ctx->update_time, ctx->avg_level);
646 nix_dump("W2: head \t\t\t%d\nW2: tail \t\t\t%d\n", ctx->head,
647 ctx->tail);
648
649 nix_dump("W3: cq_err_int_ena \t\t%d\nW3: cq_err_int \t\t\t%d",
650 ctx->cq_err_int_ena, ctx->cq_err_int);
651 nix_dump("W3: qsize \t\t\t%d\nW3: caching \t\t\t%d", ctx->qsize,
652 ctx->caching);
653 nix_dump("W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d", ctx->substream,
654 ctx->ena);
655 nix_dump("W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d", ctx->drop_ena,
656 ctx->drop);
657 nix_dump("W3: bp \t\t\t\t%d\n", ctx->bp);
658 }
659
660 int
roc_nix_queues_ctx_dump(struct roc_nix * roc_nix)661 roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)
662 {
663 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
664 int rc = -1, q, rq = nix->nb_rx_queues;
665 struct npa_aq_enq_rsp *npa_rsp;
666 struct npa_aq_enq_req *npa_aq;
667 struct dev *dev = &nix->dev;
668 int sq = nix->nb_tx_queues;
669 struct npa_lf *npa_lf;
670 volatile void *ctx;
671 uint32_t sqb_aura;
672
673 npa_lf = idev_npa_obj_get();
674 if (npa_lf == NULL)
675 return NPA_ERR_DEVICE_NOT_BOUNDED;
676
677 for (q = 0; q < rq; q++) {
678 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_CQ, q, &ctx);
679 if (rc) {
680 plt_err("Failed to get cq context");
681 goto fail;
682 }
683 nix_dump("============== port=%d cq=%d ===============",
684 roc_nix->port_id, q);
685 nix_lf_cq_dump(ctx);
686 }
687
688 for (q = 0; q < rq; q++) {
689 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, q, &ctx);
690 if (rc) {
691 plt_err("Failed to get rq context");
692 goto fail;
693 }
694 nix_dump("============== port=%d rq=%d ===============",
695 roc_nix->port_id, q);
696 if (roc_model_is_cn9k())
697 nix_cn9k_lf_rq_dump(ctx);
698 else
699 nix_lf_rq_dump(ctx);
700 }
701
702 for (q = 0; q < sq; q++) {
703 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, &ctx);
704 if (rc) {
705 plt_err("Failed to get sq context");
706 goto fail;
707 }
708 nix_dump("============== port=%d sq=%d ===============",
709 roc_nix->port_id, q);
710 if (roc_model_is_cn9k())
711 nix_cn9k_lf_sq_dump(ctx, &sqb_aura);
712 else
713 nix_lf_sq_dump(ctx, &sqb_aura);
714
715 if (!npa_lf) {
716 plt_err("NPA LF does not exist");
717 continue;
718 }
719
720 /* Dump SQB Aura minimal info */
721 npa_aq = mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
722 if (npa_aq == NULL)
723 return -ENOSPC;
724 npa_aq->aura_id = sqb_aura;
725 npa_aq->ctype = NPA_AQ_CTYPE_AURA;
726 npa_aq->op = NPA_AQ_INSTOP_READ;
727
728 rc = mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);
729 if (rc) {
730 plt_err("Failed to get sq's sqb_aura context");
731 continue;
732 }
733
734 nix_dump("\nSQB Aura W0: Pool addr\t\t0x%" PRIx64 "",
735 npa_rsp->aura.pool_addr);
736 nix_dump("SQB Aura W1: ena\t\t\t%d", npa_rsp->aura.ena);
737 nix_dump("SQB Aura W2: count\t\t%" PRIx64 "",
738 (uint64_t)npa_rsp->aura.count);
739 nix_dump("SQB Aura W3: limit\t\t%" PRIx64 "",
740 (uint64_t)npa_rsp->aura.limit);
741 nix_dump("SQB Aura W3: fc_ena\t\t%d", npa_rsp->aura.fc_ena);
742 nix_dump("SQB Aura W4: fc_addr\t\t0x%" PRIx64 "\n",
743 npa_rsp->aura.fc_addr);
744 }
745
746 fail:
747 return rc;
748 }
749
750 /* Dumps struct nix_cqe_hdr_s and union nix_rx_parse_u */
751 void
roc_nix_cqe_dump(const struct nix_cqe_hdr_s * cq)752 roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)
753 {
754 const union nix_rx_parse_u *rx =
755 (const union nix_rx_parse_u *)((const uint64_t *)cq + 1);
756 const uint64_t *sgs = (const uint64_t *)(rx + 1);
757 int i;
758
759 nix_dump("tag \t\t0x%x\tq \t\t%d\t\tnode \t\t%d\tcqe_type \t%d",
760 cq->tag, cq->q, cq->node, cq->cqe_type);
761
762 nix_dump("W0: chan \t0x%x\t\tdesc_sizem1 \t%d", rx->chan,
763 rx->desc_sizem1);
764 nix_dump("W0: imm_copy \t%d\t\texpress \t%d", rx->imm_copy,
765 rx->express);
766 nix_dump("W0: wqwd \t%d\t\terrlev \t\t%d\t\terrcode \t%d", rx->wqwd,
767 rx->errlev, rx->errcode);
768 nix_dump("W0: latype \t%d\t\tlbtype \t\t%d\t\tlctype \t\t%d",
769 rx->latype, rx->lbtype, rx->lctype);
770 nix_dump("W0: ldtype \t%d\t\tletype \t\t%d\t\tlftype \t\t%d",
771 rx->ldtype, rx->letype, rx->lftype);
772 nix_dump("W0: lgtype \t%d \t\tlhtype \t\t%d", rx->lgtype, rx->lhtype);
773
774 nix_dump("W1: pkt_lenm1 \t%d", rx->pkt_lenm1);
775 nix_dump("W1: l2m \t%d\t\tl2b \t\t%d\t\tl3m \t\t%d\tl3b \t\t%d",
776 rx->l2m, rx->l2b, rx->l3m, rx->l3b);
777 nix_dump("W1: vtag0_valid %d\t\tvtag0_gone \t%d", rx->vtag0_valid,
778 rx->vtag0_gone);
779 nix_dump("W1: vtag1_valid %d\t\tvtag1_gone \t%d", rx->vtag1_valid,
780 rx->vtag1_gone);
781 nix_dump("W1: pkind \t%d", rx->pkind);
782 nix_dump("W1: vtag0_tci \t%d\t\tvtag1_tci \t%d", rx->vtag0_tci,
783 rx->vtag1_tci);
784
785 nix_dump("W2: laflags \t%d\t\tlbflags\t\t%d\t\tlcflags \t%d",
786 rx->laflags, rx->lbflags, rx->lcflags);
787 nix_dump("W2: ldflags \t%d\t\tleflags\t\t%d\t\tlfflags \t%d",
788 rx->ldflags, rx->leflags, rx->lfflags);
789 nix_dump("W2: lgflags \t%d\t\tlhflags \t%d", rx->lgflags, rx->lhflags);
790
791 nix_dump("W3: eoh_ptr \t%d\t\twqe_aura \t%d\t\tpb_aura \t%d",
792 rx->eoh_ptr, rx->wqe_aura, rx->pb_aura);
793 nix_dump("W3: match_id \t%d", rx->match_id);
794
795 nix_dump("W4: laptr \t%d\t\tlbptr \t\t%d\t\tlcptr \t\t%d", rx->laptr,
796 rx->lbptr, rx->lcptr);
797 nix_dump("W4: ldptr \t%d\t\tleptr \t\t%d\t\tlfptr \t\t%d", rx->ldptr,
798 rx->leptr, rx->lfptr);
799 nix_dump("W4: lgptr \t%d\t\tlhptr \t\t%d", rx->lgptr, rx->lhptr);
800
801 nix_dump("W5: vtag0_ptr \t%d\t\tvtag1_ptr \t%d\t\tflow_key_alg \t%d",
802 rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);
803
804 for (i = 0; i < (rx->desc_sizem1 + 1) << 1; i++)
805 nix_dump("sg[%u] = %p", i, (void *)sgs[i]);
806 }
807
808 void
roc_nix_rq_dump(struct roc_nix_rq * rq)809 roc_nix_rq_dump(struct roc_nix_rq *rq)
810 {
811 nix_dump("nix_rq@%p", rq);
812 nix_dump(" qid = %d", rq->qid);
813 nix_dump(" aura_handle = 0x%" PRIx64 "", rq->aura_handle);
814 nix_dump(" ipsec_ena = %d", rq->ipsech_ena);
815 nix_dump(" first_skip = %d", rq->first_skip);
816 nix_dump(" later_skip = %d", rq->later_skip);
817 nix_dump(" lpb_size = %d", rq->lpb_size);
818 nix_dump(" sso_ena = %d", rq->sso_ena);
819 nix_dump(" tag_mask = %d", rq->tag_mask);
820 nix_dump(" flow_tag_width = %d", rq->flow_tag_width);
821 nix_dump(" tt = %d", rq->tt);
822 nix_dump(" hwgrp = %d", rq->hwgrp);
823 nix_dump(" vwqe_ena = %d", rq->vwqe_ena);
824 nix_dump(" vwqe_first_skip = %d", rq->vwqe_first_skip);
825 nix_dump(" vwqe_max_sz_exp = %d", rq->vwqe_max_sz_exp);
826 nix_dump(" vwqe_wait_tmo = %ld", rq->vwqe_wait_tmo);
827 nix_dump(" vwqe_aura_handle = %ld", rq->vwqe_aura_handle);
828 nix_dump(" roc_nix = %p", rq->roc_nix);
829 nix_dump(" inl_dev_refs = %d", rq->inl_dev_refs);
830 }
831
832 void
roc_nix_cq_dump(struct roc_nix_cq * cq)833 roc_nix_cq_dump(struct roc_nix_cq *cq)
834 {
835 nix_dump("nix_cq@%p", cq);
836 nix_dump(" qid = %d", cq->qid);
837 nix_dump(" qnb_desc = %d", cq->nb_desc);
838 nix_dump(" roc_nix = %p", cq->roc_nix);
839 nix_dump(" door = 0x%" PRIx64 "", cq->door);
840 nix_dump(" status = %p", cq->status);
841 nix_dump(" wdata = 0x%" PRIx64 "", cq->wdata);
842 nix_dump(" desc_base = %p", cq->desc_base);
843 nix_dump(" qmask = 0x%" PRIx32 "", cq->qmask);
844 }
845
846 void
roc_nix_sq_dump(struct roc_nix_sq * sq)847 roc_nix_sq_dump(struct roc_nix_sq *sq)
848 {
849 nix_dump("nix_sq@%p", sq);
850 nix_dump(" qid = %d", sq->qid);
851 nix_dump(" max_sqe_sz = %d", sq->max_sqe_sz);
852 nix_dump(" nb_desc = %d", sq->nb_desc);
853 nix_dump(" sqes_per_sqb_log2 = %d", sq->sqes_per_sqb_log2);
854 nix_dump(" roc_nix= %p", sq->roc_nix);
855 nix_dump(" aura_handle = 0x%" PRIx64 "", sq->aura_handle);
856 nix_dump(" nb_sqb_bufs_adj = %d", sq->nb_sqb_bufs_adj);
857 nix_dump(" nb_sqb_bufs = %d", sq->nb_sqb_bufs);
858 nix_dump(" io_addr = 0x%" PRIx64 "", sq->io_addr);
859 nix_dump(" lmt_addr = %p", sq->lmt_addr);
860 nix_dump(" sqe_mem = %p", sq->sqe_mem);
861 nix_dump(" fc = %p", sq->fc);
862 };
863
864 static uint8_t
nix_tm_reg_dump_prep(uint16_t hw_lvl,uint16_t schq,uint16_t link,uint64_t * reg,char regstr[][NIX_REG_NAME_SZ])865 nix_tm_reg_dump_prep(uint16_t hw_lvl, uint16_t schq, uint16_t link,
866 uint64_t *reg, char regstr[][NIX_REG_NAME_SZ])
867 {
868 uint8_t k = 0;
869
870 switch (hw_lvl) {
871 case NIX_TXSCH_LVL_SMQ:
872 reg[k] = NIX_AF_SMQX_CFG(schq);
873 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_SMQ[%u]_CFG",
874 schq);
875
876 reg[k] = NIX_AF_MDQX_PARENT(schq);
877 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_PARENT",
878 schq);
879
880 reg[k] = NIX_AF_MDQX_SCHEDULE(schq);
881 snprintf(regstr[k++], NIX_REG_NAME_SZ,
882 "NIX_AF_MDQ[%u]_SCHEDULE", schq);
883
884 reg[k] = NIX_AF_MDQX_PIR(schq);
885 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_PIR",
886 schq);
887
888 reg[k] = NIX_AF_MDQX_CIR(schq);
889 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_CIR",
890 schq);
891
892 reg[k] = NIX_AF_MDQX_SHAPE(schq);
893 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_SHAPE",
894 schq);
895
896 reg[k] = NIX_AF_MDQX_SW_XOFF(schq);
897 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_SW_XOFF",
898 schq);
899 break;
900 case NIX_TXSCH_LVL_TL4:
901 reg[k] = NIX_AF_TL4X_PARENT(schq);
902 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_PARENT",
903 schq);
904
905 reg[k] = NIX_AF_TL4X_TOPOLOGY(schq);
906 snprintf(regstr[k++], NIX_REG_NAME_SZ,
907 "NIX_AF_TL4[%u]_TOPOLOGY", schq);
908
909 reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
910 snprintf(regstr[k++], NIX_REG_NAME_SZ,
911 "NIX_AF_TL4[%u]_SDP_LINK_CFG", schq);
912
913 reg[k] = NIX_AF_TL4X_SCHEDULE(schq);
914 snprintf(regstr[k++], NIX_REG_NAME_SZ,
915 "NIX_AF_TL4[%u]_SCHEDULE", schq);
916
917 reg[k] = NIX_AF_TL4X_PIR(schq);
918 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_PIR",
919 schq);
920
921 reg[k] = NIX_AF_TL4X_CIR(schq);
922 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_CIR",
923 schq);
924
925 reg[k] = NIX_AF_TL4X_SHAPE(schq);
926 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_SHAPE",
927 schq);
928
929 reg[k] = NIX_AF_TL4X_SW_XOFF(schq);
930 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_SW_XOFF",
931 schq);
932 break;
933 case NIX_TXSCH_LVL_TL3:
934 reg[k] = NIX_AF_TL3X_PARENT(schq);
935 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_PARENT",
936 schq);
937
938 reg[k] = NIX_AF_TL3X_TOPOLOGY(schq);
939 snprintf(regstr[k++], NIX_REG_NAME_SZ,
940 "NIX_AF_TL3[%u]_TOPOLOGY", schq);
941
942 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
943 snprintf(regstr[k++], NIX_REG_NAME_SZ,
944 "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
945
946 reg[k] = NIX_AF_TL3X_SCHEDULE(schq);
947 snprintf(regstr[k++], NIX_REG_NAME_SZ,
948 "NIX_AF_TL3[%u]_SCHEDULE", schq);
949
950 reg[k] = NIX_AF_TL3X_PIR(schq);
951 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_PIR",
952 schq);
953
954 reg[k] = NIX_AF_TL3X_CIR(schq);
955 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_CIR",
956 schq);
957
958 reg[k] = NIX_AF_TL3X_SHAPE(schq);
959 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_SHAPE",
960 schq);
961
962 reg[k] = NIX_AF_TL3X_SW_XOFF(schq);
963 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_SW_XOFF",
964 schq);
965 break;
966 case NIX_TXSCH_LVL_TL2:
967 reg[k] = NIX_AF_TL2X_PARENT(schq);
968 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_PARENT",
969 schq);
970
971 reg[k] = NIX_AF_TL2X_TOPOLOGY(schq);
972 snprintf(regstr[k++], NIX_REG_NAME_SZ,
973 "NIX_AF_TL2[%u]_TOPOLOGY", schq);
974
975 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
976 snprintf(regstr[k++], NIX_REG_NAME_SZ,
977 "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
978
979 reg[k] = NIX_AF_TL2X_SCHEDULE(schq);
980 snprintf(regstr[k++], NIX_REG_NAME_SZ,
981 "NIX_AF_TL2[%u]_SCHEDULE", schq);
982
983 reg[k] = NIX_AF_TL2X_PIR(schq);
984 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_PIR",
985 schq);
986
987 reg[k] = NIX_AF_TL2X_CIR(schq);
988 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_CIR",
989 schq);
990
991 reg[k] = NIX_AF_TL2X_SHAPE(schq);
992 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_SHAPE",
993 schq);
994
995 reg[k] = NIX_AF_TL2X_SW_XOFF(schq);
996 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_SW_XOFF",
997 schq);
998 break;
999 case NIX_TXSCH_LVL_TL1:
1000
1001 reg[k] = NIX_AF_TL1X_TOPOLOGY(schq);
1002 snprintf(regstr[k++], NIX_REG_NAME_SZ,
1003 "NIX_AF_TL1[%u]_TOPOLOGY", schq);
1004
1005 reg[k] = NIX_AF_TL1X_SCHEDULE(schq);
1006 snprintf(regstr[k++], NIX_REG_NAME_SZ,
1007 "NIX_AF_TL1[%u]_SCHEDULE", schq);
1008
1009 reg[k] = NIX_AF_TL1X_CIR(schq);
1010 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL1[%u]_CIR",
1011 schq);
1012
1013 reg[k] = NIX_AF_TL1X_SW_XOFF(schq);
1014 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL1[%u]_SW_XOFF",
1015 schq);
1016
1017 reg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);
1018 snprintf(regstr[k++], NIX_REG_NAME_SZ,
1019 "NIX_AF_TL1[%u]_DROPPED_PACKETS", schq);
1020 break;
1021 default:
1022 break;
1023 }
1024
1025 if (k > MAX_REGS_PER_MBOX_MSG) {
1026 nix_dump("\t!!!NIX TM Registers request overflow!!!");
1027 return 0;
1028 }
1029 return k;
1030 }
1031
1032 static void
nix_tm_dump_lvl(struct nix * nix,struct nix_tm_node_list * list,uint8_t hw_lvl)1033 nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)
1034 {
1035 char regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];
1036 uint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];
1037 struct mbox *mbox = (&nix->dev)->mbox;
1038 struct nix_txschq_config *req, *rsp;
1039 const char *lvlstr, *parent_lvlstr;
1040 struct nix_tm_node *node, *parent;
1041 struct nix_tm_node *root = NULL;
1042 uint32_t schq, parent_schq;
1043 bool found = false;
1044 uint8_t j, k, rc;
1045
1046 TAILQ_FOREACH(node, list, node) {
1047 if (node->hw_lvl != hw_lvl)
1048 continue;
1049
1050 found = true;
1051 parent = node->parent;
1052 if (hw_lvl == NIX_TXSCH_LVL_CNT) {
1053 lvlstr = "SQ";
1054 schq = node->id;
1055 } else {
1056 lvlstr = nix_tm_hwlvl2str(node->hw_lvl);
1057 schq = node->hw_id;
1058 }
1059
1060 if (parent) {
1061 parent_schq = parent->hw_id;
1062 parent_lvlstr = nix_tm_hwlvl2str(parent->hw_lvl);
1063 } else if (node->hw_lvl == NIX_TXSCH_LVL_TL1) {
1064 parent_schq = nix->tx_link;
1065 parent_lvlstr = "LINK";
1066 } else {
1067 parent_schq = node->parent_hw_id;
1068 parent_lvlstr = nix_tm_hwlvl2str(node->hw_lvl + 1);
1069 }
1070
1071 nix_dump("\t(%p%s) %s_%d->%s_%d", node,
1072 node->child_realloc ? "[CR]" : "", lvlstr, schq,
1073 parent_lvlstr, parent_schq);
1074
1075 if (!(node->flags & NIX_TM_NODE_HWRES))
1076 continue;
1077
1078 /* Need to dump TL1 when root is TL2 */
1079 if (node->hw_lvl == nix->tm_root_lvl)
1080 root = node;
1081
1082 /* Dump registers only when HWRES is present */
1083 k = nix_tm_reg_dump_prep(node->hw_lvl, schq, nix->tx_link, reg,
1084 regstr);
1085 if (!k)
1086 continue;
1087
1088 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
1089 req->read = 1;
1090 req->lvl = node->hw_lvl;
1091 req->num_regs = k;
1092 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
1093 rc = mbox_process_msg(mbox, (void **)&rsp);
1094 if (!rc) {
1095 for (j = 0; j < k; j++)
1096 nix_dump("\t\t%s=0x%016" PRIx64, regstr[j],
1097 rsp->regval[j]);
1098 } else {
1099 nix_dump("\t!!!Failed to dump registers!!!");
1100 }
1101 }
1102
1103 if (found)
1104 nix_dump("\n");
1105
1106 /* Dump TL1 node data when root level is TL2 */
1107 if (root && root->hw_lvl == NIX_TXSCH_LVL_TL2) {
1108 k = nix_tm_reg_dump_prep(NIX_TXSCH_LVL_TL1, root->parent_hw_id,
1109 nix->tx_link, reg, regstr);
1110 if (!k)
1111 return;
1112
1113 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
1114 req->read = 1;
1115 req->lvl = NIX_TXSCH_LVL_TL1;
1116 req->num_regs = k;
1117 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
1118 rc = mbox_process_msg(mbox, (void **)&rsp);
1119 if (!rc) {
1120 for (j = 0; j < k; j++)
1121 nix_dump("\t\t%s=0x%016" PRIx64, regstr[j],
1122 rsp->regval[j]);
1123 } else {
1124 nix_dump("\t!!!Failed to dump registers!!!");
1125 }
1126 nix_dump("\n");
1127 }
1128 }
1129
1130 void
roc_nix_tm_dump(struct roc_nix * roc_nix)1131 roc_nix_tm_dump(struct roc_nix *roc_nix)
1132 {
1133 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1134 struct dev *dev = &nix->dev;
1135 uint8_t hw_lvl, i;
1136
1137 nix_dump("===TM hierarchy and registers dump of %s (pf:vf) (%d:%d)===",
1138 nix->pci_dev->name, dev_get_pf(dev->pf_func),
1139 dev_get_vf(dev->pf_func));
1140
1141 /* Dump all trees */
1142 for (i = 0; i < ROC_NIX_TM_TREE_MAX; i++) {
1143 nix_dump("\tTM %s:", nix_tm_tree2str(i));
1144 for (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++)
1145 nix_tm_dump_lvl(nix, &nix->trees[i], hw_lvl);
1146 }
1147
1148 /* Dump unused resources */
1149 nix_dump("\tTM unused resources:");
1150 hw_lvl = NIX_TXSCH_LVL_SMQ;
1151 for (; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1152 nix_dump("\t\ttxschq %7s num = %d",
1153 nix_tm_hwlvl2str(hw_lvl),
1154 nix_tm_resource_avail(nix, hw_lvl, false));
1155
1156 nix_bitmap_dump(nix->schq_bmp[hw_lvl]);
1157 nix_dump("\n");
1158
1159 nix_dump("\t\ttxschq_contig %7s num = %d",
1160 nix_tm_hwlvl2str(hw_lvl),
1161 nix_tm_resource_avail(nix, hw_lvl, true));
1162 nix_bitmap_dump(nix->schq_contig_bmp[hw_lvl]);
1163 nix_dump("\n");
1164 }
1165 }
1166
1167 void
roc_nix_dump(struct roc_nix * roc_nix)1168 roc_nix_dump(struct roc_nix *roc_nix)
1169 {
1170 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1171 struct dev *dev = &nix->dev;
1172 int i;
1173
1174 nix_dump("nix@%p", nix);
1175 nix_dump(" pf = %d", dev_get_pf(dev->pf_func));
1176 nix_dump(" vf = %d", dev_get_vf(dev->pf_func));
1177 nix_dump(" bar2 = 0x%" PRIx64, dev->bar2);
1178 nix_dump(" bar4 = 0x%" PRIx64, dev->bar4);
1179 nix_dump(" port_id = %d", roc_nix->port_id);
1180 nix_dump(" rss_tag_as_xor = %d", roc_nix->rss_tag_as_xor);
1181 nix_dump(" rss_tag_as_xor = %d", roc_nix->max_sqb_count);
1182 nix_dump(" outb_nb_desc = %u", roc_nix->outb_nb_desc);
1183
1184 nix_dump(" \tpci_dev = %p", nix->pci_dev);
1185 nix_dump(" \tbase = 0x%" PRIxPTR "", nix->base);
1186 nix_dump(" \tlmt_base = 0x%" PRIxPTR "", nix->lmt_base);
1187 nix_dump(" \treta_size = %d", nix->reta_sz);
1188 nix_dump(" \ttx_chan_base = %d", nix->tx_chan_base);
1189 nix_dump(" \trx_chan_base = %d", nix->rx_chan_base);
1190 nix_dump(" \tnb_rx_queues = %d", nix->nb_rx_queues);
1191 nix_dump(" \tnb_tx_queues = %d", nix->nb_tx_queues);
1192 nix_dump(" \tlso_tsov6_idx = %d", nix->lso_tsov6_idx);
1193 nix_dump(" \tlso_tsov4_idx = %d", nix->lso_tsov4_idx);
1194 nix_dump(" \tlso_udp_tun_v4v4 = %d",
1195 nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V4]);
1196 nix_dump(" \tlso_udp_tun_v4v6 = %d",
1197 nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V6]);
1198 nix_dump(" \tlso_udp_tun_v6v4 = %d",
1199 nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V4]);
1200 nix_dump(" \tlso_udp_tun_v6v6 = %d",
1201 nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V6]);
1202 nix_dump(" \tlso_tun_v4v4 = %d",
1203 nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V4]);
1204 nix_dump(" \tlso_tun_v4v6 = %d",
1205 nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V6]);
1206 nix_dump(" \tlso_tun_v6v4 = %d",
1207 nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V4]);
1208 nix_dump(" \tlso_tun_v6v6 = %d",
1209 nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V6]);
1210 nix_dump(" \tlf_rx_stats = %d", nix->lf_rx_stats);
1211 nix_dump(" \tlf_tx_stats = %d", nix->lf_tx_stats);
1212 nix_dump(" \trx_chan_cnt = %d", nix->rx_chan_cnt);
1213 nix_dump(" \ttx_chan_cnt = %d", nix->tx_chan_cnt);
1214 nix_dump(" \tcgx_links = %d", nix->cgx_links);
1215 nix_dump(" \tlbk_links = %d", nix->lbk_links);
1216 nix_dump(" \tsdp_links = %d", nix->sdp_links);
1217 nix_dump(" \ttx_link = %d", nix->tx_link);
1218 nix_dump(" \tsqb_size = %d", nix->sqb_size);
1219 nix_dump(" \tmsixoff = %d", nix->msixoff);
1220 for (i = 0; i < nix->nb_cpt_lf; i++)
1221 nix_dump(" \tcpt_msixoff[%d] = %d", i, nix->cpt_msixoff[i]);
1222 nix_dump(" \tcints = %d", nix->cints);
1223 nix_dump(" \tqints = %d", nix->qints);
1224 nix_dump(" \tsdp_link = %d", nix->sdp_link);
1225 nix_dump(" \tptp_en = %d", nix->ptp_en);
1226 nix_dump(" \trss_alg_idx = %d", nix->rss_alg_idx);
1227 nix_dump(" \ttx_pause = %d", nix->tx_pause);
1228 nix_dump(" \tinl_inb_ena = %d", nix->inl_inb_ena);
1229 nix_dump(" \tinl_outb_ena = %d", nix->inl_outb_ena);
1230 nix_dump(" \tinb_sa_base = 0x%p", nix->inb_sa_base);
1231 nix_dump(" \tinb_sa_sz = %" PRIu64, nix->inb_sa_sz);
1232 nix_dump(" \toutb_sa_base = 0x%p", nix->outb_sa_base);
1233 nix_dump(" \toutb_sa_sz = %" PRIu64, nix->outb_sa_sz);
1234 nix_dump(" \toutb_err_sso_pffunc = 0x%x", nix->outb_err_sso_pffunc);
1235 nix_dump(" \tcpt_lf_base = 0x%p", nix->cpt_lf_base);
1236 nix_dump(" \tnb_cpt_lf = %d", nix->nb_cpt_lf);
1237 nix_dump(" \tinb_inl_dev = %d", nix->inb_inl_dev);
1238 }
1239
1240 void
roc_nix_inl_dev_dump(struct roc_nix_inl_dev * roc_inl_dev)1241 roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)
1242 {
1243 struct nix_inl_dev *inl_dev =
1244 (struct nix_inl_dev *)&roc_inl_dev->reserved;
1245 struct dev *dev = &inl_dev->dev;
1246 int i;
1247
1248 nix_dump("nix_inl_dev@%p", inl_dev);
1249 nix_dump(" pf = %d", dev_get_pf(dev->pf_func));
1250 nix_dump(" vf = %d", dev_get_vf(dev->pf_func));
1251 nix_dump(" bar2 = 0x%" PRIx64, dev->bar2);
1252 nix_dump(" bar4 = 0x%" PRIx64, dev->bar4);
1253
1254 nix_dump(" \tpci_dev = %p", inl_dev->pci_dev);
1255 nix_dump(" \tnix_base = 0x%" PRIxPTR "", inl_dev->nix_base);
1256 nix_dump(" \tsso_base = 0x%" PRIxPTR "", inl_dev->sso_base);
1257 nix_dump(" \tssow_base = 0x%" PRIxPTR "", inl_dev->ssow_base);
1258 nix_dump(" \tnix_msixoff = %d", inl_dev->nix_msixoff);
1259 nix_dump(" \tsso_msixoff = %d", inl_dev->sso_msixoff);
1260 nix_dump(" \tssow_msixoff = %d", inl_dev->ssow_msixoff);
1261 nix_dump(" \tnix_cints = %d", inl_dev->cints);
1262 nix_dump(" \tnix_qints = %d", inl_dev->qints);
1263 nix_dump(" \tinb_sa_base = 0x%p", inl_dev->inb_sa_base);
1264 nix_dump(" \tinb_sa_sz = %d", inl_dev->inb_sa_sz);
1265 nix_dump(" \txaq_buf_size = %u", inl_dev->xaq_buf_size);
1266 nix_dump(" \txae_waes = %u", inl_dev->xae_waes);
1267 nix_dump(" \tiue = %u", inl_dev->iue);
1268 nix_dump(" \txaq_aura = 0x%" PRIx64, inl_dev->xaq.aura_handle);
1269 nix_dump(" \txaq_mem = 0x%p", inl_dev->xaq.mem);
1270
1271 nix_dump(" \tinl_dev_rq:");
1272 for (i = 0; i < inl_dev->nb_rqs; i++)
1273 roc_nix_rq_dump(&inl_dev->rqs[i]);
1274 }
1275