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Searched refs:high_water (Results 1 – 25 of 43) sorted by relevance

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/dpdk/drivers/net/octeontx/
H A Docteontx_ethdev_ops.c231 fc_conf->high_water = conf.high_water; in octeontx_dev_flow_ctrl_get()
254 if (fc_conf->high_water == fc->high_water && in octeontx_dev_flow_ctrl_set()
261 if (fc_conf->high_water > max_high_water || in octeontx_dev_flow_ctrl_set()
262 fc_conf->high_water < fc_conf->low_water) { in octeontx_dev_flow_ctrl_set()
269 if (fc_conf->high_water % BIT(4) || fc_conf->low_water % BIT(4)) { in octeontx_dev_flow_ctrl_set()
279 conf.high_water = fc_conf->high_water; in octeontx_dev_flow_ctrl_set()
289 fc->high_water = fc_conf->high_water; in octeontx_dev_flow_ctrl_set()
310 fc->def_highmark = fc_conf.high_water; in octeontx_dev_flow_ctrl_init()
327 fc_conf.high_water = fc->def_highmark; in octeontx_dev_flow_ctrl_fini()
H A Docteontx_ethdev.h100 uint16_t high_water; member
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_dcb.c36 if (!hw->fc.high_water[tc_num] || in txgbe_dcb_pfc_enable()
43 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { in txgbe_dcb_pfc_enable()
121 hw->fc.high_water[tc_num]) { in txgbe_dcb_pfc_enable()
124 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[tc_num]) | in txgbe_dcb_pfc_enable()
H A Dtxgbe_dcb_hw.c221 reg = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) | in txgbe_dcb_config_pfc_raptor()
H A Dtxgbe_hw.c876 hw->fc.high_water[i]) { in txgbe_fc_enable()
878 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in txgbe_fc_enable()
949 hw->fc.high_water[i]) { in txgbe_fc_enable()
952 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) | in txgbe_fc_enable()
/dpdk/drivers/net/e1000/
H A Dem_ethdev.c826 hw->fc.high_water = rx_buf_size - in em_hardware_init()
828 hw->fc.low_water = hw->fc.high_water - 1500; in em_hardware_init()
849 hw->fc.high_water = 0x5C20; in em_hardware_init()
1662 fc_conf->high_water = hw->fc.high_water; in eth_em_flow_ctrl_get()
1717 if ((fc_conf->high_water > max_high_water) || in eth_em_flow_ctrl_set()
1718 (fc_conf->high_water < fc_conf->low_water)) { in eth_em_flow_ctrl_set()
1726 hw->fc.high_water = fc_conf->high_water; in eth_em_flow_ctrl_set()
H A Digb_ethdev.c1646 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2); in igb_hardware_init()
1647 hw->fc.low_water = hw->fc.high_water - 1500; in igb_hardware_init()
3001 fc_conf->high_water = hw->fc.high_water; in eth_igb_flow_ctrl_get()
3057 if ((fc_conf->high_water > max_high_water) || in eth_igb_flow_ctrl_set()
3058 (fc_conf->high_water < fc_conf->low_water)) { in eth_igb_flow_ctrl_set()
3066 hw->fc.high_water = fc_conf->high_water; in eth_igb_flow_ctrl_set()
/dpdk/drivers/net/octeontx/base/
H A Docteontx_bgx.c374 cfg->high_water = conf.high_water; in octeontx_bgx_port_flow_ctrl_cfg()
H A Docteontx_bgx.h139 uint16_t high_water; member
/dpdk/drivers/bus/dpaa/include/
H A Dfsl_fman.h101 u32 high_water, u32 low_water, u32 bpid);
/dpdk/drivers/net/igc/
H A Digc_ethdev.c893 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2); in igc_hardware_init()
894 hw->fc.low_water = hw->fc.high_water - 1500; in igc_hardware_init()
2129 fc_conf->high_water = hw->fc.high_water; in eth_igc_flow_ctrl_get()
2178 if (fc_conf->high_water > max_high_water || in eth_igc_flow_ctrl_set()
2179 fc_conf->high_water < fc_conf->low_water) { in eth_igc_flow_ctrl_set()
2182 fc_conf->high_water, fc_conf->low_water, in eth_igc_flow_ctrl_set()
2206 hw->fc.high_water = fc_conf->high_water; in eth_igc_flow_ctrl_set()
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_82598.c400 hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
402 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
495 hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
497 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_82598()
H A Dixgbe_dcb_82598.c261 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82598()
H A Dixgbe_dcb_82599.c309 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82599()
/dpdk/drivers/net/dpaa/
H A Ddpaa_ethdev.c1333 if (fc_conf->high_water < fc_conf->low_water) { in dpaa_flow_ctrl_set()
1343 fc_conf->high_water, in dpaa_flow_ctrl_set()
1353 net_fc->high_water = fc_conf->high_water; in dpaa_flow_ctrl_set()
1375 fc_conf->high_water = net_fc->high_water; in dpaa_flow_ctrl_get()
/dpdk/drivers/net/ngbe/base/
H A Dngbe_hw.c837 if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) { in ngbe_fc_enable()
839 hw->fc.low_water >= hw->fc.high_water) { in ngbe_fc_enable()
907 hw->fc.high_water) { in ngbe_fc_enable()
910 fcrth = NGBE_FCWTRHI_TH(hw->fc.high_water) | in ngbe_fc_enable()
H A Dngbe_type.h108 u32 high_water; /* Flow Ctrl High-water */ member
/dpdk/drivers/bus/dpaa/base/fman/
H A Dfman_hw.c399 fman_if_set_fc_threshold(struct fman_if *fm_if, u32 high_water, in fman_if_set_fc_threshold() argument
409 return bm_pool_set_hw_threshold(bpid, low_water, high_water); in fman_if_set_fc_threshold()
/dpdk/drivers/net/ngbe/
H A Dngbe_ethdev.c389 hw->fc.high_water = NGBE_FC_XOFF_HITH; in eth_ngbe_dev_init()
2250 fc_conf->high_water = hw->fc.high_water; in ngbe_flow_ctrl_get()
2311 if (fc_conf->high_water > max_high_water || in ngbe_flow_ctrl_set()
2312 fc_conf->high_water < fc_conf->low_water) { in ngbe_flow_ctrl_set()
2320 hw->fc.high_water = fc_conf->high_water; in ngbe_flow_ctrl_set()
/dpdk/drivers/net/txgbe/
H A Dtxgbe_ethdev.c636 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH; in eth_txgbe_dev_init()
3192 fc_conf->high_water = hw->fc.high_water[0]; in txgbe_flow_ctrl_get()
3254 if (fc_conf->high_water > max_high_water || in txgbe_flow_ctrl_set()
3255 fc_conf->high_water < fc_conf->low_water) { in txgbe_flow_ctrl_set()
3263 hw->fc.high_water[0] = fc_conf->high_water; in txgbe_flow_ctrl_set()
3314 if (pfc_conf->fc.high_water > max_high_water || in txgbe_priority_flow_ctrl_set()
3315 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) { in txgbe_priority_flow_ctrl_set()
3325 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; in txgbe_priority_flow_ctrl_set()
/dpdk/drivers/net/axgbe/
H A Daxgbe_ethdev.h517 uint32_t high_water[AXGBE_PRIORITY_QUEUES]; member
H A Daxgbe_ethdev.c1264 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); in axgbe_flow_ctrl_get()
1277 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; in axgbe_flow_ctrl_get()
1278 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; in axgbe_flow_ctrl_get()
1298 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); in axgbe_flow_ctrl_set()
1352 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); in axgbe_priority_flow_ctrl_set()
/dpdk/drivers/net/ixgbe/
H A Dixgbe_ethdev.c1148 hw->fc.high_water[i] = IXGBE_FC_HI; in eth_ixgbe_dev_init()
4731 fc_conf->high_water = hw->fc.high_water[0]; in ixgbe_flow_ctrl_get()
4800 if ((fc_conf->high_water > max_high_water) || in ixgbe_flow_ctrl_set()
4801 (fc_conf->high_water < fc_conf->low_water)) { in ixgbe_flow_ctrl_set()
4809 hw->fc.high_water[0] = fc_conf->high_water; in ixgbe_flow_ctrl_set()
4854 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { in ixgbe_dcb_pfc_enable_generic()
4933 hw->fc.high_water[tc_num]) { in ixgbe_dcb_pfc_enable_generic()
4936 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_pfc_enable_generic()
5005 if ((pfc_conf->fc.high_water > max_high_water) || in ixgbe_priority_flow_ctrl_set()
5006 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { in ixgbe_priority_flow_ctrl_set()
[all …]
/dpdk/drivers/net/igc/base/
H A Digc_hw.h885 u32 high_water; /* Flow control high-water mark */ member
/dpdk/drivers/net/e1000/base/
H A De1000_hw.h862 u32 high_water; /* Flow control high-water mark */ member

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