| /llvm-project-15.0.7/llvm/tools/llvm-cfi-verify/lib/ |
| H A D | FileAnalysis.h | 78 struct Instr { struct 80 MCInst Instruction; // Instruction. argument 81 uint64_t InstructionSize; // Size of this instruction. argument 82 bool Valid; // Is this a valid instruction? If false, Instr::Instruction is argument
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| H A D | GraphBuilder.h | 44 using Instr = llvm::cfi_verify::FileAnalysis::Instr; variable
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| /llvm-project-15.0.7/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | ELF_aarch64.cpp | 189 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local 200 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local 211 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local 222 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local 233 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local 244 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local 255 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local 266 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local 277 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
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| H A D | MachO_arm64.cpp | 331 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local 375 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local 395 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local 409 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
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| /llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/ |
| H A D | SerialSnippetGenerator.cpp | 38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr, in computeAliasingInstructions() 71 static ExecutionMode getExecutionModes(const Instruction &Instr, in getExecutionModes() 133 const Instruction &Instr = Variant.getInstr(); in appendCodeTemplates() local
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| H A D | Target.h | 120 virtual Error randomizeTargetMCOperand(const Instruction &Instr, in randomizeTargetMCOperand() 131 virtual bool allowAsBackToBack(const Instruction &Instr) const { in allowAsBackToBack() 139 generateInstructionVariants(const Instruction &Instr, in generateInstructionVariants()
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| H A D | ParallelSnippetGenerator.cpp | 83 getVariablesWithTiedOperands(const Instruction &Instr) { in getVariablesWithTiedOperands() 160 const Instruction &Instr = Variant.getInstr(); in generateCodeTemplates() local
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| H A D | CodeTemplate.cpp | 18 InstructionTemplate::InstructionTemplate(const Instruction *Instr) in InstructionTemplate()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFeatures.h | 24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT()
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| /llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/ |
| H A D | Target.cpp | 61 static const char *isInvalidMemoryInstr(const Instruction &Instr) { in isInvalidMemoryInstr() 196 static const char *isInvalidOpcode(const Instruction &Instr) { in isInvalidOpcode() 235 static unsigned getX86FPFlags(const Instruction &Instr) { in getX86FPFlags() 250 const Instruction &Instr, const BitVector &ForbiddenRegisters, in generateLEATemplatesCommon() 327 const Instruction &Instr = Variant.getInstr(); in generateCodeTemplates() local 387 const Instruction &Instr = Variant.getInstr(); in generateCodeTemplates() local 812 const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue, in randomizeTargetMCOperand() 909 const Instruction &Instr, unsigned MaxConfigsPerOpcode) const { in generateInstructionVariants() argument
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 742 struct Instr { in select() struct 743 unsigned Opcode; in select() 744 Register Def, LHS, RHS; in select() 745 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS) in select() argument 748 bool hasImm() const { in select()
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| /llvm-project-15.0.7/llvm/utils/TableGen/GlobalISel/ |
| H A D | GIMatchDagPredicate.cpp | 27 GIMatchDagContext &Ctx, StringRef Name, const CodeGenInstruction &Instr) in GIMatchDagOpcodePredicate() 44 for (const CodeGenInstruction *Instr : Instrs) { in printDescription() local
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| H A D | GIMatchDagPredicate.h | 84 const CodeGenInstruction &Instr; variable 109 void addOpcode(const CodeGenInstruction *Instr) { Instrs.push_back(Instr); } in addOpcode()
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| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/ |
| H A D | SnippetGeneratorTest.cpp | 39 const Instruction &Instr = State.getIC().getInstr(Opcode); in checkAndGetCodeTemplates() local 89 const Instruction &Instr = State.getIC().getInstr(Mips::XOR); in TEST_F() local
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| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/ |
| H A D | SnippetGeneratorTest.cpp | 46 const Instruction &Instr = State.getIC().getInstr(Opcode); in checkAndGetCodeTemplates() local 148 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F() local 205 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F() local 336 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F() local 351 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F() local 414 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F() local
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RemoveRedundantDebugValues.cpp | 138 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsForwardScan() local 193 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsBackwardScan() local
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| H A D | MachineSSAContext.cpp | 48 if (auto *Instr = MRI->getUniqueVRegDef(Value)) { in print() local
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| /llvm-project-15.0.7/llvm/include/llvm/ExecutionEngine/JITLink/ |
| H A D | aarch64.h | 52 inline bool isLoadStoreImm12(uint32_t Instr) { in isLoadStoreImm12() 63 inline unsigned getPageOffset12Shift(uint32_t Instr) { in getPageOffset12Shift() 79 inline bool isMoveWideImm16(uint32_t Instr) { in isMoveWideImm16() 88 inline unsigned getMoveWide16Shift(uint32_t Instr) { in getMoveWide16Shift()
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| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | VectorUtils.h | 615 InterleaveGroup(InstTy *Instr, int32_t Stride, Align Alignment) in InterleaveGroup() 634 bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign) { in insertMember() 686 uint32_t getIndex(const InstTy *Instr) const { in getIndex() 788 bool isInterleaved(Instruction *Instr) const { in isInterleaved() 796 getInterleaveGroup(const Instruction *Instr) const { in getInterleaveGroup() 868 createInterleaveGroup(Instruction *Instr, int Stride, Align Alignment) { in createInterleaveGroup()
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| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | AsmDump.cpp | 39 void dumpCFI(const BinaryFunction &BF, const MCInst &Instr, AsmPrinter &MAP) { in dumpCFI() 59 const MCInst &Instr, const std::string &BranchLabel) { in dumpJumpTableFdata() 73 const MCInst &Instr, const std::string &BranchLabel) { in dumpTailCallFdata()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyDebugValueManager.cpp | 22 MachineInstr *Instr) { in WebAssemblyDebugValueManager()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() 132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXProxyRegErasure.cpp | 109 void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr, in replaceRegisterUsage()
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| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/PowerPC/ |
| H A D | SnippetGeneratorTest.cpp | 39 const Instruction &Instr = State.getIC().getInstr(Opcode); in checkAndGetCodeTemplates() local
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| /llvm-project-15.0.7/bolt/lib/Core/ |
| H A D | Exceptions.cpp | 532 const CFIProgram::Instruction &Instr) { in fillCFIInfoFor() 665 for (const CFIProgram::Instruction &Instr : CurFDE.getLinkedCIE()->cfis()) in fillCFIInfoFor() local 669 for (const CFIProgram::Instruction &Instr : CurFDE.cfis()) in fillCFIInfoFor() local
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