| /llvm-project-15.0.7/llvm/lib/Transforms/IPO/ |
| H A D | Annotation2Metadata.cpp | 60 auto *Bitcast = dyn_cast<ConstantExpr>(OpC->getOperand(0)); in convertAnnotation2Metadata() local
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| H A D | FunctionSpecialization.cpp | 148 if (auto *Bitcast = dyn_cast<BitCastInst>(User)) { in getPromotableAlloca() local
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86LowerAMXType.cpp | 235 void X86LowerAMXType::combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast) { in combineLoadBitcast()
260 void X86LowerAMXType::combineBitcastStore(BitCastInst *Bitcast, StoreInst *ST) { in combineBitcastStore()
292 bool X86LowerAMXType::transformBitcast(BitCastInst *Bitcast) { in transformBitcast()
356 auto *Bitcast = dyn_cast<BitCastInst>(&Inst); in visit() local
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPreLegalizerCombiner.cpp | 145 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16() local
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| H A D | AMDGPURegisterBankInfo.cpp | 1730 auto Bitcast = B.buildBitcast(S32, Src); in unpackV2S16ToS32() local
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 443 auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)}); in legalizeCustom() local
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| H A D | MipsISelLowering.cpp | 5002 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass); in emitSTR_D() local
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.h | 54 Bitcast, enumerator
|
| H A D | LegalizerInfo.h | 73 Bitcast, enumerator
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| /llvm-project-15.0.7/llvm/lib/Transforms/Coroutines/ |
| H A D | Coroutines.cpp | 61 auto *Bitcast = in makeSubFnCall() local
|
| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 163 Bitcast, enumerator
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| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | CodeExtractor.cpp | 549 Instruction *Bitcast = cast<Instruction>(U); in findAllocas() local
582 Instruction *Bitcast = cast<Instruction>(U); in findAllocas() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1132 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore() local
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | LoadStoreVectorizer.cpp | 1273 Value *Bitcast = in vectorizeLoadChain() local
|
| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2443 SDValue Bitcast = N->getOperand(0); in performVECTOR_SHUFFLECombine() local
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2145 SDValue Bitcast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, A); in LowerFROUND32() local
|
| /llvm-project-15.0.7/llvm/unittests/Frontend/ |
| H A D | OpenMPIRBuilderTest.cpp | 4147 auto *Bitcast = in TEST_F() local
4323 auto *Bitcast = findSingleUserInBlock<BitCastInst>(AddReduction->getArg(0), in TEST_F() local
|
| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 2968 auto *Bitcast = dyn_cast<BitCastInst>(Cmp.getOperand(0)); in foldICmpBitCast() local
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15304 SDNode *Bitcast = *Trunc->use_begin(); in PerformDAGCombine() local
17247 SDValue Bitcast = DCI.DAG.getBitcast(MVT::v2i64, Op0.getOperand(0)); in combineTRUNCATE() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 17719 SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN); in PerformMinMaxCombine() local
17760 SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN); in PerformMinMaxCombine() local
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2984 SDValue Bitcast = DAG.getBitcast(IntVT, FloatVal); in lowerCTLZ_CTTZ_ZERO_UNDEF() local
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 19472 SDValue Bitcast = Insert.getOperand(1); in performDupLane128Combine() local
|