S390x: emit new instructions added in z17 (#12319)

* s390x: Emit instructions from MIE4 & VXRS_EXT3 on z17

This emits & tests a bunch of instructions:
* from Miscellaneous-Instruction-Extensions

S390x: emit new instructions added in z17 (#12319)

* s390x: Emit instructions from MIE4 & VXRS_EXT3 on z17

This emits & tests a bunch of instructions:
* from Miscellaneous-Instruction-Extensions Facility 4:
* CLZ, 64bit
* CTZ, 64bit
* from Vector-Enhancements Facility 3:
* 32x4, 64x2 & 128x1 variants of the following:
* Divide
* Remainder
* 64x2 & 128x1 multiply variants
* 128x1 vaiants of:
* Compare
* CLZ
* CTZ
* Max
* Min
* Average
* Negation
* Evaluate

Co-authored-by: Jimmy Brisson <[email protected]>

* s390x: Emit vector blend on z17

* Rename x86_blendv to blendv

Now that s390x implements blendv as well, we should refer to
the instruction without the x86 prefix.

---------

Co-authored-by: Ulrich Weigand <[email protected]>

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Cranelift: fuzzgen: avoid generating `preserve_all`-ABI functions with return values. (#12489)

Fixes #12488.

fuzzgen: Don't generate float unordered vector ops on aarch64 (#12442)

This is a refinement of the change in #12196 to fix fuzzgen on oss-fuzz
because aarch64 doesn't currently have lowerings for th

fuzzgen: Don't generate float unordered vector ops on aarch64 (#12442)

This is a refinement of the change in #12196 to fix fuzzgen on oss-fuzz
because aarch64 doesn't currently have lowerings for these float
orderings, only the scalar versions were added in #12196.

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Add cranelift fcmp ult, ule, ugt, uge for aarch64 (#12196)

* Run cranelift fcmp ord and uno tests on aarch64

FloatCC::Ordered and FloatCC:Unordered are already implemented for
aarch64, so these can

Add cranelift fcmp ult, ule, ugt, uge for aarch64 (#12196)

* Run cranelift fcmp ord and uno tests on aarch64

FloatCC::Ordered and FloatCC:Unordered are already implemented for
aarch64, so these can be enabled as they already pass.

* Run more cranelift fcmp tests on aarch64

These currently fail as they are not implemented yet.

* Add cranelift fcmp ult, ule, ugt, uge for aarch64

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Cranelift: make all non-tail, non-indirect calls patchable, and rename patchable ABI to `preserve_all`. (#12160)

* Cranelift: make all non-tail, non-indirect calls patchable, and rename patchable AB

Cranelift: make all non-tail, non-indirect calls patchable, and rename patchable ABI to `preserve_all`. (#12160)

* Cranelift: make all non-tail, non-indirect calls patchable, and rename patchable ABI to `preserve_all`.

As discussed in this week's Cranelift meeting, we've discovered a need
to generalize the `patchable_call` mechanism and corresponding
`patchable` ABI slightly. In particular, we will need patchable
`try_call` callsites as well in order to allow breakpoint handlers to
throw exceptions (desirable functionality eventually) and have this work
in the presence of inlining. Also, it's just a nice generalization to
say that patchability is an orthogonal dimension to the call ABI and the
other restrictions we initially imposed, and works as long as the basic
requirement (no return values) is met.

This also renames the `patchable` ABI to `preserve_all`, to make it
clear that its purpose is actually orthogonal, and it can be used
independently of patchable callsites. It also deletes the `cold` ABI,
which never actually did anything and is misleading in the presence of
an actual cold-ish (subzero temperature, actually) ABI like
`preserve_all`.

* Review feedback.

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Cranelift: support fuzzing `patchable_call`. (#12118)

This allows the opcode for call-format instructions and verifies that we
are calling it with the patchable ABI.

Fixes https://oss-fuzz.com/test

Cranelift: support fuzzing `patchable_call`. (#12118)

This allows the opcode for call-format instructions and verifies that we
are calling it with the patchable ABI.

Fixes https://oss-fuzz.com/testcase-detail/6014638929281024.

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Never use `colocated` symbols in `cranelift-fuzzgen` (#11872)

As I've just discovered it turns out that all functions are in their own
mmap, and mmaps aren't guaranteed to be anywhere near one anoth

Never use `colocated` symbols in `cranelift-fuzzgen` (#11872)

As I've just discovered it turns out that all functions are in their own
mmap, and mmaps aren't guaranteed to be anywhere near one another. This
means that functions cannot ever be `colocated` and must always have
absolute relocations to one another.

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Don't fuzz `sequence_point` in `cranelift-fuzzgen` (#11831)

It's not implemented in the interpreter right now so add it to the list
of opcodes to exclude.

Couple cleanups to the flags/settings handling in Cranelift (#11744)

* Remove unused shared flags

* Get rid of predicate settings

They were important in the old backend framework, but with the new

Couple cleanups to the flags/settings handling in Cranelift (#11744)

* Remove unused shared flags

* Get rid of predicate settings

They were important in the old backend framework, but with the new
backend framework if we need a combination of multiple settings, that
can just be done as a regular extractor doing &&. This simplifies the
settings implementation.

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Cranelift: add get_exception_handler_address. (#11629)

* Cranelift: add get_exception_handler_address.

This is designed to enable applications such as #11592 that use
alternative unwinding mechanis

Cranelift: add get_exception_handler_address. (#11629)

* Cranelift: add get_exception_handler_address.

This is designed to enable applications such as #11592 that use
alternative unwinding mechanisms that may not necessarily want to walk a
stack and look up exception tables. The idea is that whenever it would
be valid to resume to an exception handler that is active on the stack,
we can provide the same PC as a first-class runtime value that would be
found in the exception table for the given handler edge. A "custom"
resume step can then use this PC as a resume-point as long as it follows
the relevant exception ABI (i.e.: restore SP, FP, any other saved
registers that the exception ABI specifies, and provide appropriate
payload value(s)).

Handlers are associated with edges out of `try_call`s (or
`try_call_indirect`s); and edges specifically, not blocks, because there
could be multiple out-edges to one block. The instruction thus takes the
block that contains the try-call and an immediate that indexes its
exceptional edges.

This CLIF instruction required a bit of infrastructure to (i) allow
naming raw blocks, not just block calls, as instruction arguments, and
(ii) allow getting the MachLabel for any other lowered block during
lowering. But given that, the lowerings themselves are straightforward
uses of MachBuffer labels to fix-up PC-relative address-loading
instructions (e.g., `LEA` or `ADR` or `AUIPC`+`ADDI`).

* Review feedback.

* Review feedback: more tests.

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