[TableGen][X86] Add Size field to X86MemOperand class

Set Size appropriately in operand definitions and query it for dumping memory
operand size table `getMemOperandSize` (follow-up use D126116) and

[TableGen][X86] Add Size field to X86MemOperand class

Set Size appropriately in operand definitions and query it for dumping memory
operand size table `getMemOperandSize` (follow-up use D126116) and
`X86Disassembler::getMemOperandSize`.

Excerpt from a produced `getMemOperandSize` table for X86:

```
static int getMemOperandSize(int OpType) {
switch (OpType) {
default: return 0;
case OpTypes::i8mem:
case OpTypes::i8mem_NOREX:
return 8;

case OpTypes::f16mem:
case OpTypes::i16mem:
return 16;

case OpTypes::f32mem:
case OpTypes::i32mem:
return 32;
...
```

Reviewed By: skan, pengfei

Differential Revision: https://reviews.llvm.org/D127787

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[X86] Fix handling of maskmovdqu in x32 differently

This reverts the functional changes of D103427 but keeps its tests, and
and reimplements the functionality by reusing the existing 32-bit
MASKMOVD

[X86] Fix handling of maskmovdqu in x32 differently

This reverts the functional changes of D103427 but keeps its tests, and
and reimplements the functionality by reusing the existing 32-bit
MASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review.
These instructions were previously predicated on Not64BitMode. This
reimplementation restores the disassembly of a class of instructions,
which will see a test added in followup patch D122449.

These instructions are in 64-bit mode special cased in
X86MCInstLower::Lower, because we use flags with one meaning for subtly
different things: we have an AdSize32 class which indicates both that
the instruction needs a 0x67 prefix and that the text form of the
instruction implies a 0x67 prefix. These instructions are special in
needing a 0x67 prefix but having a text form that does *not* imply a
0x67 prefix, so we encode this in MCInst as an instruction that has an
explicit address size override.

Note that originally VMASKMOVDQU64 was special cased to be excluded from
disassembly, as we cannot distinguish between VMASKMOVDQU and
VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or
close enough to it, at the MCInst level that it does not matter which we
use. Because VMASKMOVDQU now receives special casing, even though it
does not make a difference in the current implementation, as a
precaution VMASKMOVDQU is excluded from disassembly rather than
VMASKMOVDQU64.

Reviewed By: RKSimon, skan

Differential Revision: https://reviews.llvm.org/D122540

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[X86][tablgen] Extract common functions in X86EVEX2VEXTablesEmitter.cpp and X86FoldTablesEmitter.cpp to avoid duplicated code. NFC

[X86][tablgen] Rename some fields for RecognizableInstrBase to align with fields in TD file. NFC

The comment for `HasVEX_L` is updated.

[X86][tablgen] Rename field hasREX_WPrefix to hasREX_W for X86Inst. NFC

To make it more like hasVEX_L and hasEVEX_K, etc.

[X86][tablgen] Refine the class RecognizableInstr. NFCI

1. Add comments to explain why we set `isAsmParserOnly` for XACQUIRE and XRELEASE
2. Check `X86Inst` in the constructor of `RecognizableInstrB

[X86][tablgen] Refine the class RecognizableInstr. NFCI

1. Add comments to explain why we set `isAsmParserOnly` for XACQUIRE and XRELEASE
2. Check `X86Inst` in the constructor of `RecognizableInstrBase` so that
we can avoid the case where one of it's field is not initialized but
accessed by user. (e.g. in X86EVEX2VEXTablesEmitter.cpp)
3. Move `Rec` from `RecognizableInstrBase` to `RecognizableInstr` to reduce
size of `RecognizableInstrBase`
4. Remove out-of-date comments for shouldBeEmitted() (filter() was removed)
5. Add a basic field `IsAsmParserOnly` and remove the field
`ShouldBeEmitted` b/c we can deduce it w/ little overhead

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[X86][tablgen] Set ShouldBeEmitted to false when isAsmParserOnly is true. NFCI

In fact, an instruction can not be emitted to disassemble table when
`isAsmParserOnly` is true, so `isAsmParserOnly=tru

[X86][tablgen] Set ShouldBeEmitted to false when isAsmParserOnly is true. NFCI

In fact, an instruction can not be emitted to disassemble table when
`isAsmParserOnly` is true, so `isAsmParserOnly=true` implies
`ShouldBeEmitted=false`.

We check `isAsmParserOnly` in X86FoldTablesEmitter.cpp at a early stage
b/c none of them is foldable.

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[X86][tablgen] Use initializer list for some fields of RecognizableInstr*. NFC

Also, some code in constructor of `RecognizableInstrBase` is formatted.

[X86][tablgen] Move fields Name, Is64Bit, Is32Bit, Operands from RecognizableInstrBase to RecognizableInstr, NFCI

These four fields are not used by any user of `RecognizableInstrBase`,
so we can mov

[X86][tablgen] Move fields Name, Is64Bit, Is32Bit, Operands from RecognizableInstrBase to RecognizableInstr, NFCI

These four fields are not used by any user of `RecognizableInstrBase`,
so we can move them to `RecognizableInstr` to avoid unnecessary
construction.

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[X86][tablgen] Add class RecognizableInstrBase to simplify X86 code, NFCI

[X86][tablgen] Add interface getMnemonic to namespace X86Disassembler, NFCI

Address comments in D122477 b/c `getMnemonic` is common to X86 and may be
used in more than one place.

Prevent comparison with wider type in loop condition

This change fixes the code violations flagged in AMD compute CodeQL scan - "comparison-with-wider-type"

Differential Revision: https://reviews.l

Prevent comparison with wider type in loop condition

This change fixes the code violations flagged in AMD compute CodeQL scan - "comparison-with-wider-type"

Differential Revision: https://reviews.llvm.org/D122447

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Avoid comparisons between types of different widths in a loop condition to prevent the loop from behaving unexpectedly

This change fixes the code violations flagged in AMD compute CodeQL scan -
Quer

Avoid comparisons between types of different widths in a loop condition to prevent the loop from behaving unexpectedly

This change fixes the code violations flagged in AMD compute CodeQL scan -
Query Description: "Comparisons between types of different widths in a loop condition can cause the loop to behave unexpectedly."

Differential Revision: https://reviews.llvm.org/D120355

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Cleanup llvm/utils/TableGen headers

Based on the output of include-what-you-use.
It's an utility directory, so no much impact on other code areas.

clang++ -E -Iinclude -I../llvm/include ../llvm/ut

Cleanup llvm/utils/TableGen headers

Based on the output of include-what-you-use.
It's an utility directory, so no much impact on other code areas.

clang++ -E -Iinclude -I../llvm/include ../llvm/utils/TableGen/*.cpp -std=c++14 -fno-rtti -fno-exceptions | wc -l
before: 4327274
after: 4316190

Related discourse thread: https://llvm.discourse.group/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D118466

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[tools, utils] Use StringRef::contains (NFC)

[X86][NFC] Remove unused encoding string: VK[1/2/4/8/16]PAIR

This is also a bug. The VK[1/2/4/8/16]PAIR here should be VK[1/2/4/8/16]Pair which has its
custom PrintMethod and ParserMatchClass. Howev

[X86][NFC] Remove unused encoding string: VK[1/2/4/8/16]PAIR

This is also a bug. The VK[1/2/4/8/16]PAIR here should be VK[1/2/4/8/16]Pair which has its
custom PrintMethod and ParserMatchClass. However we don't have any instructions using vvvv
and ModR/M.REG field so this issue is not exposed.

Differential Revision: https://reviews.llvm.org/D109564

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[X86] AVX512FP16 instructions enabling 1/6

1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.co

[X86] AVX512FP16 instructions enabling 1/6

1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105263

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[X86] Fix handling of maskmovdqu in X32

The maskmovdqu instruction is an odd one: it has a 32-bit and a 64-bit
variant, the former using EDI, the latter RDI, but the use of the
register is implicit.

[X86] Fix handling of maskmovdqu in X32

The maskmovdqu instruction is an odd one: it has a 32-bit and a 64-bit
variant, the former using EDI, the latter RDI, but the use of the
register is implicit. In 64-bit mode, a 0x67 prefix can be used to get
the version using EDI, but there is no way to express this in
assembly in a single instruction, the only way is with an explicit
addr32.

This change adds support for the instruction. When generating assembly
text, that explicit addr32 will be added. When not generating assembly
text, it will be kept as a single instruction and will be emitted with
that 0x67 prefix. When parsing assembly text, it will be re-parsed as
ADDR32 followed by MASKMOVDQU64, which still results in the correct
bytes when converted to machine code.

The same applies to vmaskmovdqu as well.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103427

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[X86] Avoid std::string creation in RecognizableInstr constructor. NFCI.

The value names in byteFromRec calls are compile time constants - just create StringRef directly instead of via std::string.

[X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register.

This matches GNU assembler behavior. Operand size is determined
only from the destination register.

[X86-64] Support Intel AMX instructions

Summary:
INTEL ADVANCED MATRIX EXTENSIONS (AMX).
AMX is a new programming paradigm, it has a set of 2-dimensional registers
(TILES) representing sub-arrays fr

[X86-64] Support Intel AMX instructions

Summary:
INTEL ADVANCED MATRIX EXTENSIONS (AMX).
AMX is a new programming paradigm, it has a set of 2-dimensional registers
(TILES) representing sub-arrays from a larger 2-dimensional memory image and
operate on TILES.

Spec can be found in Chapter 3 here https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewers: LuoYuanke, annita.zhang, pengfei, RKSimon, xiangzhangllvm

Reviewed By: xiangzhangllvm

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82705

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[X86] Ignore bits 2:0 of the modrm byte when disassembling lfence, mfence, and sfence.

These are documented as using modrm byte of 0xe8, 0xf0, and 0xf8
respectively. But hardware ignore bits 2:0. So

[X86] Ignore bits 2:0 of the modrm byte when disassembling lfence, mfence, and sfence.

These are documented as using modrm byte of 0xe8, 0xf0, and 0xf8
respectively. But hardware ignore bits 2:0. So 0xe9-0xef is treated
the same as 0xe8. Similar for the other two.

Fixing this required adding 8 new formats to the X86 instructions
to convey this information. Could have gotten away with 3, but
adding all 8 made for a more logical conversion from format to
modrm encoding.

I renumbered the format encodings to keep the register modrm
formats grouped together.

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[X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix.

isPrefix was added to support the patches to align b

[X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix.

isPrefix was added to support the patches to align branches.
it relies on a switch over instruction names.

This moves those opcodes to a new format so the information is
tablegen and we can just check for a specific value in some bits
in TSFlags instead.

I've left the other function in place for now so that the
existing patches in phabricator will still work. I'll work with
the owner to get them migrated.

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Make llvm::StringRef to std::string conversions explicit.

This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly m

Make llvm::StringRef to std::string conversions explicit.

This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly mechanical from a custom clang-tidy check, with a lot of
manual fixups. It uncovers a lot of minor inefficiencies.

This doesn't actually modify StringRef yet, I'll do that in a follow-up.

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[ms] [X86] Use "P" modifier on all branch-target operands in inline X86 assembly.

Summary:
Extend D71677 to apply to all branch-target operands, rather than special-casing call instructions.

Also a

[ms] [X86] Use "P" modifier on all branch-target operands in inline X86 assembly.

Summary:
Extend D71677 to apply to all branch-target operands, rather than special-casing call instructions.

Also add a regression test for llvm.org/PR44272, since this finishes fixing it.

Reviewers: thakis, rnk

Reviewed By: thakis

Subscribers: merge_guards_bot, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D72417

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