1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include <string> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) { 28 std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant); 29 StringRef Mnemonic(AsmString); 30 // Extract a mnemonic assuming it's separated by \t 31 Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; }); 32 33 // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic. 34 // Replace it with "CC" in-place. 35 size_t CondPos = Mnemonic.find("${cond}"); 36 if (CondPos != StringRef::npos) 37 Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC"); 38 return Mnemonic.upper(); 39 } 40 41 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 42 /// Useful for switch statements and the like. 43 /// 44 /// @param init - A reference to the BitsInit to be decoded. 45 /// @return - The field, with the first bit in the BitsInit as the lowest 46 /// order bit. 47 static uint8_t byteFromBitsInit(BitsInit &init) { 48 int width = init.getNumBits(); 49 50 assert(width <= 8 && "Field is too large for uint8_t!"); 51 52 int index; 53 uint8_t mask = 0x01; 54 55 uint8_t ret = 0; 56 57 for (index = 0; index < width; index++) { 58 if (cast<BitInit>(init.getBit(index))->getValue()) 59 ret |= mask; 60 61 mask <<= 1; 62 } 63 64 return ret; 65 } 66 67 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 68 /// name of the field. 69 /// 70 /// @param rec - The record from which to extract the value. 71 /// @param name - The name of the field in the record. 72 /// @return - The field, as translated by byteFromBitsInit(). 73 static uint8_t byteFromRec(const Record* rec, StringRef name) { 74 BitsInit* bits = rec->getValueAsBitsInit(name); 75 return byteFromBitsInit(*bits); 76 } 77 78 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) { 79 Rec = insn.TheDef; 80 Name = std::string(Rec->getName()); 81 82 if (!Rec->isSubClassOf("X86Inst")) { 83 ShouldBeEmitted = false; 84 return; 85 } 86 87 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 88 OpMap = byteFromRec(Rec, "OpMapBits"); 89 Opcode = byteFromRec(Rec, "Opcode"); 90 Form = byteFromRec(Rec, "FormBits"); 91 Encoding = byteFromRec(Rec, "OpEncBits"); 92 93 OpSize = byteFromRec(Rec, "OpSizeBits"); 94 AdSize = byteFromRec(Rec, "AdSizeBits"); 95 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 96 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 97 HasVEX_W = Rec->getValueAsBit("HasVEX_W"); 98 IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W"); 99 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 100 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 101 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 102 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 103 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 104 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 105 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 106 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 107 108 Name = std::string(Rec->getName()); 109 110 Operands = &insn.Operands.OperandList; 111 112 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 113 114 EncodeRC = HasEVEX_B && 115 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 116 117 // Check for 64-bit inst which does not require REX 118 Is32Bit = false; 119 Is64Bit = false; 120 // FIXME: Is there some better way to check for In64BitMode? 121 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 122 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 123 if (Predicates[i]->getName().contains("Not64Bit") || 124 Predicates[i]->getName().contains("In32Bit")) { 125 Is32Bit = true; 126 break; 127 } 128 if (Predicates[i]->getName().contains("In64Bit")) { 129 Is64Bit = true; 130 break; 131 } 132 } 133 134 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 135 ShouldBeEmitted = false; 136 return; 137 } 138 139 ShouldBeEmitted = true; 140 } 141 142 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 143 const CodeGenInstruction &insn, 144 InstrUID uid) 145 : RecognizableInstrBase(insn) { 146 UID = uid; 147 Spec = &tables.specForUID(UID); 148 } 149 150 void RecognizableInstr::processInstr(DisassemblerTables &tables, 151 const CodeGenInstruction &insn, 152 InstrUID uid) 153 { 154 // Ignore "asm parser only" instructions. 155 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 156 return; 157 158 RecognizableInstr recogInstr(tables, insn, uid); 159 160 if (recogInstr.shouldBeEmitted()) { 161 recogInstr.emitInstructionSpecifier(); 162 recogInstr.emitDecodePath(tables); 163 } 164 } 165 166 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 167 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 168 (HasEVEX_KZ ? n##_KZ : \ 169 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 170 171 InstructionContext RecognizableInstr::insnContext() const { 172 InstructionContext insnContext; 173 174 if (Encoding == X86Local::EVEX) { 175 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 176 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 177 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 178 } 179 // VEX_L & VEX_W 180 if (!EncodeRC && HasVEX_LPrefix && HasVEX_W) { 181 if (OpPrefix == X86Local::PD) 182 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 183 else if (OpPrefix == X86Local::XS) 184 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 185 else if (OpPrefix == X86Local::XD) 186 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 187 else if (OpPrefix == X86Local::PS) 188 insnContext = EVEX_KB(IC_EVEX_L_W); 189 else { 190 errs() << "Instruction does not use a prefix: " << Name << "\n"; 191 llvm_unreachable("Invalid prefix"); 192 } 193 } else if (!EncodeRC && HasVEX_LPrefix) { 194 // VEX_L 195 if (OpPrefix == X86Local::PD) 196 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 197 else if (OpPrefix == X86Local::XS) 198 insnContext = EVEX_KB(IC_EVEX_L_XS); 199 else if (OpPrefix == X86Local::XD) 200 insnContext = EVEX_KB(IC_EVEX_L_XD); 201 else if (OpPrefix == X86Local::PS) 202 insnContext = EVEX_KB(IC_EVEX_L); 203 else { 204 errs() << "Instruction does not use a prefix: " << Name << "\n"; 205 llvm_unreachable("Invalid prefix"); 206 } 207 } else if (!EncodeRC && HasEVEX_L2Prefix && HasVEX_W) { 208 // EVEX_L2 & VEX_W 209 if (OpPrefix == X86Local::PD) 210 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 211 else if (OpPrefix == X86Local::XS) 212 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 213 else if (OpPrefix == X86Local::XD) 214 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 215 else if (OpPrefix == X86Local::PS) 216 insnContext = EVEX_KB(IC_EVEX_L2_W); 217 else { 218 errs() << "Instruction does not use a prefix: " << Name << "\n"; 219 llvm_unreachable("Invalid prefix"); 220 } 221 } else if (!EncodeRC && HasEVEX_L2Prefix) { 222 // EVEX_L2 223 if (OpPrefix == X86Local::PD) 224 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 225 else if (OpPrefix == X86Local::XD) 226 insnContext = EVEX_KB(IC_EVEX_L2_XD); 227 else if (OpPrefix == X86Local::XS) 228 insnContext = EVEX_KB(IC_EVEX_L2_XS); 229 else if (OpPrefix == X86Local::PS) 230 insnContext = EVEX_KB(IC_EVEX_L2); 231 else { 232 errs() << "Instruction does not use a prefix: " << Name << "\n"; 233 llvm_unreachable("Invalid prefix"); 234 } 235 } 236 else if (HasVEX_W) { 237 // VEX_W 238 if (OpPrefix == X86Local::PD) 239 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 240 else if (OpPrefix == X86Local::XS) 241 insnContext = EVEX_KB(IC_EVEX_W_XS); 242 else if (OpPrefix == X86Local::XD) 243 insnContext = EVEX_KB(IC_EVEX_W_XD); 244 else if (OpPrefix == X86Local::PS) 245 insnContext = EVEX_KB(IC_EVEX_W); 246 else { 247 errs() << "Instruction does not use a prefix: " << Name << "\n"; 248 llvm_unreachable("Invalid prefix"); 249 } 250 } 251 // No L, no W 252 else if (OpPrefix == X86Local::PD) 253 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 254 else if (OpPrefix == X86Local::XD) 255 insnContext = EVEX_KB(IC_EVEX_XD); 256 else if (OpPrefix == X86Local::XS) 257 insnContext = EVEX_KB(IC_EVEX_XS); 258 else if (OpPrefix == X86Local::PS) 259 insnContext = EVEX_KB(IC_EVEX); 260 else { 261 errs() << "Instruction does not use a prefix: " << Name << "\n"; 262 llvm_unreachable("Invalid prefix"); 263 } 264 /// eof EVEX 265 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 266 if (HasVEX_LPrefix && HasVEX_W) { 267 if (OpPrefix == X86Local::PD) 268 insnContext = IC_VEX_L_W_OPSIZE; 269 else if (OpPrefix == X86Local::XS) 270 insnContext = IC_VEX_L_W_XS; 271 else if (OpPrefix == X86Local::XD) 272 insnContext = IC_VEX_L_W_XD; 273 else if (OpPrefix == X86Local::PS) 274 insnContext = IC_VEX_L_W; 275 else { 276 errs() << "Instruction does not use a prefix: " << Name << "\n"; 277 llvm_unreachable("Invalid prefix"); 278 } 279 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 280 insnContext = IC_VEX_L_OPSIZE; 281 else if (OpPrefix == X86Local::PD && HasVEX_W) 282 insnContext = IC_VEX_W_OPSIZE; 283 else if (OpPrefix == X86Local::PD && Is64Bit && 284 AdSize == X86Local::AdSize32) 285 insnContext = IC_64BIT_VEX_OPSIZE_ADSIZE; 286 else if (OpPrefix == X86Local::PD && Is64Bit) 287 insnContext = IC_64BIT_VEX_OPSIZE; 288 else if (OpPrefix == X86Local::PD) 289 insnContext = IC_VEX_OPSIZE; 290 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 291 insnContext = IC_VEX_L_XS; 292 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 293 insnContext = IC_VEX_L_XD; 294 else if (HasVEX_W && OpPrefix == X86Local::XS) 295 insnContext = IC_VEX_W_XS; 296 else if (HasVEX_W && OpPrefix == X86Local::XD) 297 insnContext = IC_VEX_W_XD; 298 else if (HasVEX_W && OpPrefix == X86Local::PS) 299 insnContext = IC_VEX_W; 300 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 301 insnContext = IC_VEX_L; 302 else if (OpPrefix == X86Local::XD) 303 insnContext = IC_VEX_XD; 304 else if (OpPrefix == X86Local::XS) 305 insnContext = IC_VEX_XS; 306 else if (OpPrefix == X86Local::PS) 307 insnContext = IC_VEX; 308 else { 309 errs() << "Instruction does not use a prefix: " << Name << "\n"; 310 llvm_unreachable("Invalid prefix"); 311 } 312 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 313 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 314 insnContext = IC_64BIT_REXW_OPSIZE; 315 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 316 insnContext = IC_64BIT_REXW_ADSIZE; 317 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 318 insnContext = IC_64BIT_XD_OPSIZE; 319 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 320 insnContext = IC_64BIT_XS_OPSIZE; 321 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 322 insnContext = IC_64BIT_OPSIZE_ADSIZE; 323 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 324 insnContext = IC_64BIT_OPSIZE_ADSIZE; 325 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 326 insnContext = IC_64BIT_OPSIZE; 327 else if (AdSize == X86Local::AdSize32) 328 insnContext = IC_64BIT_ADSIZE; 329 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 330 insnContext = IC_64BIT_REXW_XS; 331 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 332 insnContext = IC_64BIT_REXW_XD; 333 else if (OpPrefix == X86Local::XD) 334 insnContext = IC_64BIT_XD; 335 else if (OpPrefix == X86Local::XS) 336 insnContext = IC_64BIT_XS; 337 else if (HasREX_WPrefix) 338 insnContext = IC_64BIT_REXW; 339 else 340 insnContext = IC_64BIT; 341 } else { 342 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 343 insnContext = IC_XD_OPSIZE; 344 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 345 insnContext = IC_XS_OPSIZE; 346 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 347 insnContext = IC_XD_ADSIZE; 348 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 349 insnContext = IC_XS_ADSIZE; 350 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 351 insnContext = IC_OPSIZE_ADSIZE; 352 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 353 insnContext = IC_OPSIZE_ADSIZE; 354 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 355 insnContext = IC_OPSIZE; 356 else if (AdSize == X86Local::AdSize16) 357 insnContext = IC_ADSIZE; 358 else if (OpPrefix == X86Local::XD) 359 insnContext = IC_XD; 360 else if (OpPrefix == X86Local::XS) 361 insnContext = IC_XS; 362 else 363 insnContext = IC; 364 } 365 366 return insnContext; 367 } 368 369 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 370 // The scaling factor for AVX512 compressed displacement encoding is an 371 // instruction attribute. Adjust the ModRM encoding type to include the 372 // scale for compressed displacement. 373 if ((encoding != ENCODING_RM && 374 encoding != ENCODING_VSIB && 375 encoding != ENCODING_SIB) ||CD8_Scale == 0) 376 return; 377 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 378 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 379 (encoding == ENCODING_SIB) || 380 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 381 "Invalid CDisp scaling"); 382 } 383 384 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 385 unsigned &physicalOperandIndex, 386 unsigned numPhysicalOperands, 387 const unsigned *operandMapping, 388 OperandEncoding (*encodingFromString) 389 (const std::string&, 390 uint8_t OpSize)) { 391 if (optional) { 392 if (physicalOperandIndex >= numPhysicalOperands) 393 return; 394 } else { 395 assert(physicalOperandIndex < numPhysicalOperands); 396 } 397 398 while (operandMapping[operandIndex] != operandIndex) { 399 Spec->operands[operandIndex].encoding = ENCODING_DUP; 400 Spec->operands[operandIndex].type = 401 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 402 ++operandIndex; 403 } 404 405 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 406 407 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize); 408 // Adjust the encoding type for an operand based on the instruction. 409 adjustOperandEncoding(encoding); 410 Spec->operands[operandIndex].encoding = encoding; 411 Spec->operands[operandIndex].type = 412 typeFromString(std::string(typeName), HasREX_WPrefix, OpSize); 413 414 ++operandIndex; 415 ++physicalOperandIndex; 416 } 417 418 void RecognizableInstr::emitInstructionSpecifier() { 419 Spec->name = Name; 420 421 Spec->insnContext = insnContext(); 422 423 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 424 425 unsigned numOperands = OperandList.size(); 426 unsigned numPhysicalOperands = 0; 427 428 // operandMapping maps from operands in OperandList to their originals. 429 // If operandMapping[i] != i, then the entry is a duplicate. 430 unsigned operandMapping[X86_MAX_OPERANDS]; 431 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 432 433 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 434 if (!OperandList[operandIndex].Constraints.empty()) { 435 const CGIOperandList::ConstraintInfo &Constraint = 436 OperandList[operandIndex].Constraints[0]; 437 if (Constraint.isTied()) { 438 operandMapping[operandIndex] = operandIndex; 439 operandMapping[Constraint.getTiedOperand()] = operandIndex; 440 } else { 441 ++numPhysicalOperands; 442 operandMapping[operandIndex] = operandIndex; 443 } 444 } else { 445 ++numPhysicalOperands; 446 operandMapping[operandIndex] = operandIndex; 447 } 448 } 449 450 #define HANDLE_OPERAND(class) \ 451 handleOperand(false, \ 452 operandIndex, \ 453 physicalOperandIndex, \ 454 numPhysicalOperands, \ 455 operandMapping, \ 456 class##EncodingFromString); 457 458 #define HANDLE_OPTIONAL(class) \ 459 handleOperand(true, \ 460 operandIndex, \ 461 physicalOperandIndex, \ 462 numPhysicalOperands, \ 463 operandMapping, \ 464 class##EncodingFromString); 465 466 // operandIndex should always be < numOperands 467 unsigned operandIndex = 0; 468 // physicalOperandIndex should always be < numPhysicalOperands 469 unsigned physicalOperandIndex = 0; 470 471 #ifndef NDEBUG 472 // Given the set of prefix bits, how many additional operands does the 473 // instruction have? 474 unsigned additionalOperands = 0; 475 if (HasVEX_4V) 476 ++additionalOperands; 477 if (HasEVEX_K) 478 ++additionalOperands; 479 #endif 480 481 switch (Form) { 482 default: llvm_unreachable("Unhandled form"); 483 case X86Local::PrefixByte: 484 return; 485 case X86Local::RawFrmSrc: 486 HANDLE_OPERAND(relocation); 487 return; 488 case X86Local::RawFrmDst: 489 HANDLE_OPERAND(relocation); 490 return; 491 case X86Local::RawFrmDstSrc: 492 HANDLE_OPERAND(relocation); 493 HANDLE_OPERAND(relocation); 494 return; 495 case X86Local::RawFrm: 496 // Operand 1 (optional) is an address or immediate. 497 assert(numPhysicalOperands <= 1 && 498 "Unexpected number of operands for RawFrm"); 499 HANDLE_OPTIONAL(relocation) 500 break; 501 case X86Local::RawFrmMemOffs: 502 // Operand 1 is an address. 503 HANDLE_OPERAND(relocation); 504 break; 505 case X86Local::AddRegFrm: 506 // Operand 1 is added to the opcode. 507 // Operand 2 (optional) is an address. 508 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 509 "Unexpected number of operands for AddRegFrm"); 510 HANDLE_OPERAND(opcodeModifier) 511 HANDLE_OPTIONAL(relocation) 512 break; 513 case X86Local::AddCCFrm: 514 // Operand 1 (optional) is an address or immediate. 515 assert(numPhysicalOperands == 2 && 516 "Unexpected number of operands for AddCCFrm"); 517 HANDLE_OPERAND(relocation) 518 HANDLE_OPERAND(opcodeModifier) 519 break; 520 case X86Local::MRMDestReg: 521 // Operand 1 is a register operand in the R/M field. 522 // - In AVX512 there may be a mask operand here - 523 // Operand 2 is a register operand in the Reg/Opcode field. 524 // - In AVX, there is a register operand in the VEX.vvvv field here - 525 // Operand 3 (optional) is an immediate. 526 assert(numPhysicalOperands >= 2 + additionalOperands && 527 numPhysicalOperands <= 3 + additionalOperands && 528 "Unexpected number of operands for MRMDestRegFrm"); 529 530 HANDLE_OPERAND(rmRegister) 531 if (HasEVEX_K) 532 HANDLE_OPERAND(writemaskRegister) 533 534 if (HasVEX_4V) 535 // FIXME: In AVX, the register below becomes the one encoded 536 // in ModRMVEX and the one above the one in the VEX.VVVV field 537 HANDLE_OPERAND(vvvvRegister) 538 539 HANDLE_OPERAND(roRegister) 540 HANDLE_OPTIONAL(immediate) 541 break; 542 case X86Local::MRMDestMem: 543 case X86Local::MRMDestMemFSIB: 544 // Operand 1 is a memory operand (possibly SIB-extended) 545 // Operand 2 is a register operand in the Reg/Opcode field. 546 // - In AVX, there is a register operand in the VEX.vvvv field here - 547 // Operand 3 (optional) is an immediate. 548 assert(numPhysicalOperands >= 2 + additionalOperands && 549 numPhysicalOperands <= 3 + additionalOperands && 550 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 551 552 HANDLE_OPERAND(memory) 553 554 if (HasEVEX_K) 555 HANDLE_OPERAND(writemaskRegister) 556 557 if (HasVEX_4V) 558 // FIXME: In AVX, the register below becomes the one encoded 559 // in ModRMVEX and the one above the one in the VEX.VVVV field 560 HANDLE_OPERAND(vvvvRegister) 561 562 HANDLE_OPERAND(roRegister) 563 HANDLE_OPTIONAL(immediate) 564 break; 565 case X86Local::MRMSrcReg: 566 // Operand 1 is a register operand in the Reg/Opcode field. 567 // Operand 2 is a register operand in the R/M field. 568 // - In AVX, there is a register operand in the VEX.vvvv field here - 569 // Operand 3 (optional) is an immediate. 570 // Operand 4 (optional) is an immediate. 571 572 assert(numPhysicalOperands >= 2 + additionalOperands && 573 numPhysicalOperands <= 4 + additionalOperands && 574 "Unexpected number of operands for MRMSrcRegFrm"); 575 576 HANDLE_OPERAND(roRegister) 577 578 if (HasEVEX_K) 579 HANDLE_OPERAND(writemaskRegister) 580 581 if (HasVEX_4V) 582 // FIXME: In AVX, the register below becomes the one encoded 583 // in ModRMVEX and the one above the one in the VEX.VVVV field 584 HANDLE_OPERAND(vvvvRegister) 585 586 HANDLE_OPERAND(rmRegister) 587 HANDLE_OPTIONAL(immediate) 588 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 589 break; 590 case X86Local::MRMSrcReg4VOp3: 591 assert(numPhysicalOperands == 3 && 592 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 593 HANDLE_OPERAND(roRegister) 594 HANDLE_OPERAND(rmRegister) 595 HANDLE_OPERAND(vvvvRegister) 596 break; 597 case X86Local::MRMSrcRegOp4: 598 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 599 "Unexpected number of operands for MRMSrcRegOp4Frm"); 600 HANDLE_OPERAND(roRegister) 601 HANDLE_OPERAND(vvvvRegister) 602 HANDLE_OPERAND(immediate) // Register in imm[7:4] 603 HANDLE_OPERAND(rmRegister) 604 HANDLE_OPTIONAL(immediate) 605 break; 606 case X86Local::MRMSrcRegCC: 607 assert(numPhysicalOperands == 3 && 608 "Unexpected number of operands for MRMSrcRegCC"); 609 HANDLE_OPERAND(roRegister) 610 HANDLE_OPERAND(rmRegister) 611 HANDLE_OPERAND(opcodeModifier) 612 break; 613 case X86Local::MRMSrcMem: 614 case X86Local::MRMSrcMemFSIB: 615 // Operand 1 is a register operand in the Reg/Opcode field. 616 // Operand 2 is a memory operand (possibly SIB-extended) 617 // - In AVX, there is a register operand in the VEX.vvvv field here - 618 // Operand 3 (optional) is an immediate. 619 620 assert(numPhysicalOperands >= 2 + additionalOperands && 621 numPhysicalOperands <= 4 + additionalOperands && 622 "Unexpected number of operands for MRMSrcMemFrm"); 623 624 HANDLE_OPERAND(roRegister) 625 626 if (HasEVEX_K) 627 HANDLE_OPERAND(writemaskRegister) 628 629 if (HasVEX_4V) 630 // FIXME: In AVX, the register below becomes the one encoded 631 // in ModRMVEX and the one above the one in the VEX.VVVV field 632 HANDLE_OPERAND(vvvvRegister) 633 634 HANDLE_OPERAND(memory) 635 HANDLE_OPTIONAL(immediate) 636 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 637 break; 638 case X86Local::MRMSrcMem4VOp3: 639 assert(numPhysicalOperands == 3 && 640 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 641 HANDLE_OPERAND(roRegister) 642 HANDLE_OPERAND(memory) 643 HANDLE_OPERAND(vvvvRegister) 644 break; 645 case X86Local::MRMSrcMemOp4: 646 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 647 "Unexpected number of operands for MRMSrcMemOp4Frm"); 648 HANDLE_OPERAND(roRegister) 649 HANDLE_OPERAND(vvvvRegister) 650 HANDLE_OPERAND(immediate) // Register in imm[7:4] 651 HANDLE_OPERAND(memory) 652 HANDLE_OPTIONAL(immediate) 653 break; 654 case X86Local::MRMSrcMemCC: 655 assert(numPhysicalOperands == 3 && 656 "Unexpected number of operands for MRMSrcMemCC"); 657 HANDLE_OPERAND(roRegister) 658 HANDLE_OPERAND(memory) 659 HANDLE_OPERAND(opcodeModifier) 660 break; 661 case X86Local::MRMXrCC: 662 assert(numPhysicalOperands == 2 && 663 "Unexpected number of operands for MRMXrCC"); 664 HANDLE_OPERAND(rmRegister) 665 HANDLE_OPERAND(opcodeModifier) 666 break; 667 case X86Local::MRMr0: 668 // Operand 1 is a register operand in the R/M field. 669 HANDLE_OPERAND(roRegister) 670 break; 671 case X86Local::MRMXr: 672 case X86Local::MRM0r: 673 case X86Local::MRM1r: 674 case X86Local::MRM2r: 675 case X86Local::MRM3r: 676 case X86Local::MRM4r: 677 case X86Local::MRM5r: 678 case X86Local::MRM6r: 679 case X86Local::MRM7r: 680 // Operand 1 is a register operand in the R/M field. 681 // Operand 2 (optional) is an immediate or relocation. 682 // Operand 3 (optional) is an immediate. 683 assert(numPhysicalOperands >= 0 + additionalOperands && 684 numPhysicalOperands <= 3 + additionalOperands && 685 "Unexpected number of operands for MRMnr"); 686 687 if (HasVEX_4V) 688 HANDLE_OPERAND(vvvvRegister) 689 690 if (HasEVEX_K) 691 HANDLE_OPERAND(writemaskRegister) 692 HANDLE_OPTIONAL(rmRegister) 693 HANDLE_OPTIONAL(relocation) 694 HANDLE_OPTIONAL(immediate) 695 break; 696 case X86Local::MRMXmCC: 697 assert(numPhysicalOperands == 2 && 698 "Unexpected number of operands for MRMXm"); 699 HANDLE_OPERAND(memory) 700 HANDLE_OPERAND(opcodeModifier) 701 break; 702 case X86Local::MRMXm: 703 case X86Local::MRM0m: 704 case X86Local::MRM1m: 705 case X86Local::MRM2m: 706 case X86Local::MRM3m: 707 case X86Local::MRM4m: 708 case X86Local::MRM5m: 709 case X86Local::MRM6m: 710 case X86Local::MRM7m: 711 // Operand 1 is a memory operand (possibly SIB-extended) 712 // Operand 2 (optional) is an immediate or relocation. 713 assert(numPhysicalOperands >= 1 + additionalOperands && 714 numPhysicalOperands <= 2 + additionalOperands && 715 "Unexpected number of operands for MRMnm"); 716 717 if (HasVEX_4V) 718 HANDLE_OPERAND(vvvvRegister) 719 if (HasEVEX_K) 720 HANDLE_OPERAND(writemaskRegister) 721 HANDLE_OPERAND(memory) 722 HANDLE_OPTIONAL(relocation) 723 break; 724 case X86Local::RawFrmImm8: 725 // operand 1 is a 16-bit immediate 726 // operand 2 is an 8-bit immediate 727 assert(numPhysicalOperands == 2 && 728 "Unexpected number of operands for X86Local::RawFrmImm8"); 729 HANDLE_OPERAND(immediate) 730 HANDLE_OPERAND(immediate) 731 break; 732 case X86Local::RawFrmImm16: 733 // operand 1 is a 16-bit immediate 734 // operand 2 is a 16-bit immediate 735 HANDLE_OPERAND(immediate) 736 HANDLE_OPERAND(immediate) 737 break; 738 case X86Local::MRM0X: 739 case X86Local::MRM1X: 740 case X86Local::MRM2X: 741 case X86Local::MRM3X: 742 case X86Local::MRM4X: 743 case X86Local::MRM5X: 744 case X86Local::MRM6X: 745 case X86Local::MRM7X: 746 #define MAP(from, to) case X86Local::MRM_##from: 747 X86_INSTR_MRM_MAPPING 748 #undef MAP 749 HANDLE_OPTIONAL(relocation) 750 break; 751 } 752 753 #undef HANDLE_OPERAND 754 #undef HANDLE_OPTIONAL 755 } 756 757 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 758 // Special cases where the LLVM tables are not complete 759 760 #define MAP(from, to) \ 761 case X86Local::MRM_##from: 762 763 llvm::Optional<OpcodeType> opcodeType; 764 switch (OpMap) { 765 default: llvm_unreachable("Invalid map!"); 766 case X86Local::OB: opcodeType = ONEBYTE; break; 767 case X86Local::TB: opcodeType = TWOBYTE; break; 768 case X86Local::T8: opcodeType = THREEBYTE_38; break; 769 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 770 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 771 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 772 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 773 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 774 case X86Local::T_MAP5: opcodeType = MAP5; break; 775 case X86Local::T_MAP6: opcodeType = MAP6; break; 776 } 777 778 std::unique_ptr<ModRMFilter> filter; 779 switch (Form) { 780 default: llvm_unreachable("Invalid form!"); 781 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 782 case X86Local::RawFrm: 783 case X86Local::AddRegFrm: 784 case X86Local::RawFrmMemOffs: 785 case X86Local::RawFrmSrc: 786 case X86Local::RawFrmDst: 787 case X86Local::RawFrmDstSrc: 788 case X86Local::RawFrmImm8: 789 case X86Local::RawFrmImm16: 790 case X86Local::AddCCFrm: 791 case X86Local::PrefixByte: 792 filter = std::make_unique<DumbFilter>(); 793 break; 794 case X86Local::MRMDestReg: 795 case X86Local::MRMSrcReg: 796 case X86Local::MRMSrcReg4VOp3: 797 case X86Local::MRMSrcRegOp4: 798 case X86Local::MRMSrcRegCC: 799 case X86Local::MRMXrCC: 800 case X86Local::MRMXr: 801 filter = std::make_unique<ModFilter>(true); 802 break; 803 case X86Local::MRMDestMem: 804 case X86Local::MRMDestMemFSIB: 805 case X86Local::MRMSrcMem: 806 case X86Local::MRMSrcMemFSIB: 807 case X86Local::MRMSrcMem4VOp3: 808 case X86Local::MRMSrcMemOp4: 809 case X86Local::MRMSrcMemCC: 810 case X86Local::MRMXmCC: 811 case X86Local::MRMXm: 812 filter = std::make_unique<ModFilter>(false); 813 break; 814 case X86Local::MRM0r: case X86Local::MRM1r: 815 case X86Local::MRM2r: case X86Local::MRM3r: 816 case X86Local::MRM4r: case X86Local::MRM5r: 817 case X86Local::MRM6r: case X86Local::MRM7r: 818 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 819 break; 820 case X86Local::MRM0X: case X86Local::MRM1X: 821 case X86Local::MRM2X: case X86Local::MRM3X: 822 case X86Local::MRM4X: case X86Local::MRM5X: 823 case X86Local::MRM6X: case X86Local::MRM7X: 824 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); 825 break; 826 case X86Local::MRMr0: 827 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); 828 break; 829 case X86Local::MRM0m: case X86Local::MRM1m: 830 case X86Local::MRM2m: case X86Local::MRM3m: 831 case X86Local::MRM4m: case X86Local::MRM5m: 832 case X86Local::MRM6m: case X86Local::MRM7m: 833 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 834 break; 835 X86_INSTR_MRM_MAPPING 836 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 837 break; 838 } // switch (Form) 839 840 uint8_t opcodeToSet = Opcode; 841 842 unsigned AddressSize = 0; 843 switch (AdSize) { 844 case X86Local::AdSize16: AddressSize = 16; break; 845 case X86Local::AdSize32: AddressSize = 32; break; 846 case X86Local::AdSize64: AddressSize = 64; break; 847 } 848 849 assert(opcodeType && "Opcode type not set"); 850 assert(filter && "Filter not set"); 851 852 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 853 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 854 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) { 855 uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16; 856 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 857 858 uint8_t currentOpcode; 859 860 for (currentOpcode = opcodeToSet; 861 currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode) 862 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 863 UID, Is32Bit, OpPrefix == 0, 864 IgnoresVEX_L || EncodeRC, 865 IgnoresVEX_W, AddressSize); 866 } else { 867 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 868 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 869 IgnoresVEX_W, AddressSize); 870 } 871 872 #undef MAP 873 } 874 875 #define TYPE(str, type) if (s == str) return type; 876 OperandType RecognizableInstr::typeFromString(const std::string &s, 877 bool hasREX_WPrefix, 878 uint8_t OpSize) { 879 if(hasREX_WPrefix) { 880 // For instructions with a REX_W prefix, a declared 32-bit register encoding 881 // is special. 882 TYPE("GR32", TYPE_R32) 883 } 884 if(OpSize == X86Local::OpSize16) { 885 // For OpSize16 instructions, a declared 16-bit register or 886 // immediate encoding is special. 887 TYPE("GR16", TYPE_Rv) 888 } else if(OpSize == X86Local::OpSize32) { 889 // For OpSize32 instructions, a declared 32-bit register or 890 // immediate encoding is special. 891 TYPE("GR32", TYPE_Rv) 892 } 893 TYPE("i16mem", TYPE_M) 894 TYPE("i16imm", TYPE_IMM) 895 TYPE("i16i8imm", TYPE_IMM) 896 TYPE("GR16", TYPE_R16) 897 TYPE("GR16orGR32orGR64", TYPE_R16) 898 TYPE("i32mem", TYPE_M) 899 TYPE("i32imm", TYPE_IMM) 900 TYPE("i32i8imm", TYPE_IMM) 901 TYPE("GR32", TYPE_R32) 902 TYPE("GR32orGR64", TYPE_R32) 903 TYPE("i64mem", TYPE_M) 904 TYPE("i64i32imm", TYPE_IMM) 905 TYPE("i64i8imm", TYPE_IMM) 906 TYPE("GR64", TYPE_R64) 907 TYPE("i8mem", TYPE_M) 908 TYPE("i8imm", TYPE_IMM) 909 TYPE("u4imm", TYPE_UIMM8) 910 TYPE("u8imm", TYPE_UIMM8) 911 TYPE("i16u8imm", TYPE_UIMM8) 912 TYPE("i32u8imm", TYPE_UIMM8) 913 TYPE("i64u8imm", TYPE_UIMM8) 914 TYPE("GR8", TYPE_R8) 915 TYPE("VR128", TYPE_XMM) 916 TYPE("VR128X", TYPE_XMM) 917 TYPE("f128mem", TYPE_M) 918 TYPE("f256mem", TYPE_M) 919 TYPE("f512mem", TYPE_M) 920 TYPE("FR128", TYPE_XMM) 921 TYPE("FR64", TYPE_XMM) 922 TYPE("FR64X", TYPE_XMM) 923 TYPE("f64mem", TYPE_M) 924 TYPE("sdmem", TYPE_M) 925 TYPE("FR16X", TYPE_XMM) 926 TYPE("FR32", TYPE_XMM) 927 TYPE("FR32X", TYPE_XMM) 928 TYPE("f32mem", TYPE_M) 929 TYPE("f16mem", TYPE_M) 930 TYPE("ssmem", TYPE_M) 931 TYPE("shmem", TYPE_M) 932 TYPE("RST", TYPE_ST) 933 TYPE("RSTi", TYPE_ST) 934 TYPE("i128mem", TYPE_M) 935 TYPE("i256mem", TYPE_M) 936 TYPE("i512mem", TYPE_M) 937 TYPE("i64i32imm_brtarget", TYPE_REL) 938 TYPE("i16imm_brtarget", TYPE_REL) 939 TYPE("i32imm_brtarget", TYPE_REL) 940 TYPE("ccode", TYPE_IMM) 941 TYPE("AVX512RC", TYPE_IMM) 942 TYPE("brtarget32", TYPE_REL) 943 TYPE("brtarget16", TYPE_REL) 944 TYPE("brtarget8", TYPE_REL) 945 TYPE("f80mem", TYPE_M) 946 TYPE("lea64_32mem", TYPE_M) 947 TYPE("lea64mem", TYPE_M) 948 TYPE("VR64", TYPE_MM64) 949 TYPE("i64imm", TYPE_IMM) 950 TYPE("anymem", TYPE_M) 951 TYPE("opaquemem", TYPE_M) 952 TYPE("sibmem", TYPE_MSIB) 953 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 954 TYPE("DEBUG_REG", TYPE_DEBUGREG) 955 TYPE("CONTROL_REG", TYPE_CONTROLREG) 956 TYPE("srcidx8", TYPE_SRCIDX) 957 TYPE("srcidx16", TYPE_SRCIDX) 958 TYPE("srcidx32", TYPE_SRCIDX) 959 TYPE("srcidx64", TYPE_SRCIDX) 960 TYPE("dstidx8", TYPE_DSTIDX) 961 TYPE("dstidx16", TYPE_DSTIDX) 962 TYPE("dstidx32", TYPE_DSTIDX) 963 TYPE("dstidx64", TYPE_DSTIDX) 964 TYPE("offset16_8", TYPE_MOFFS) 965 TYPE("offset16_16", TYPE_MOFFS) 966 TYPE("offset16_32", TYPE_MOFFS) 967 TYPE("offset32_8", TYPE_MOFFS) 968 TYPE("offset32_16", TYPE_MOFFS) 969 TYPE("offset32_32", TYPE_MOFFS) 970 TYPE("offset32_64", TYPE_MOFFS) 971 TYPE("offset64_8", TYPE_MOFFS) 972 TYPE("offset64_16", TYPE_MOFFS) 973 TYPE("offset64_32", TYPE_MOFFS) 974 TYPE("offset64_64", TYPE_MOFFS) 975 TYPE("VR256", TYPE_YMM) 976 TYPE("VR256X", TYPE_YMM) 977 TYPE("VR512", TYPE_ZMM) 978 TYPE("VK1", TYPE_VK) 979 TYPE("VK1WM", TYPE_VK) 980 TYPE("VK2", TYPE_VK) 981 TYPE("VK2WM", TYPE_VK) 982 TYPE("VK4", TYPE_VK) 983 TYPE("VK4WM", TYPE_VK) 984 TYPE("VK8", TYPE_VK) 985 TYPE("VK8WM", TYPE_VK) 986 TYPE("VK16", TYPE_VK) 987 TYPE("VK16WM", TYPE_VK) 988 TYPE("VK32", TYPE_VK) 989 TYPE("VK32WM", TYPE_VK) 990 TYPE("VK64", TYPE_VK) 991 TYPE("VK64WM", TYPE_VK) 992 TYPE("VK1Pair", TYPE_VK_PAIR) 993 TYPE("VK2Pair", TYPE_VK_PAIR) 994 TYPE("VK4Pair", TYPE_VK_PAIR) 995 TYPE("VK8Pair", TYPE_VK_PAIR) 996 TYPE("VK16Pair", TYPE_VK_PAIR) 997 TYPE("vx64mem", TYPE_MVSIBX) 998 TYPE("vx128mem", TYPE_MVSIBX) 999 TYPE("vx256mem", TYPE_MVSIBX) 1000 TYPE("vy128mem", TYPE_MVSIBY) 1001 TYPE("vy256mem", TYPE_MVSIBY) 1002 TYPE("vx64xmem", TYPE_MVSIBX) 1003 TYPE("vx128xmem", TYPE_MVSIBX) 1004 TYPE("vx256xmem", TYPE_MVSIBX) 1005 TYPE("vy128xmem", TYPE_MVSIBY) 1006 TYPE("vy256xmem", TYPE_MVSIBY) 1007 TYPE("vy512xmem", TYPE_MVSIBY) 1008 TYPE("vz256mem", TYPE_MVSIBZ) 1009 TYPE("vz512mem", TYPE_MVSIBZ) 1010 TYPE("BNDR", TYPE_BNDR) 1011 TYPE("TILE", TYPE_TMM) 1012 errs() << "Unhandled type string " << s << "\n"; 1013 llvm_unreachable("Unhandled type string"); 1014 } 1015 #undef TYPE 1016 1017 #define ENCODING(str, encoding) if (s == str) return encoding; 1018 OperandEncoding 1019 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1020 uint8_t OpSize) { 1021 if(OpSize != X86Local::OpSize16) { 1022 // For instructions without an OpSize prefix, a declared 16-bit register or 1023 // immediate encoding is special. 1024 ENCODING("i16imm", ENCODING_IW) 1025 } 1026 ENCODING("i32i8imm", ENCODING_IB) 1027 ENCODING("AVX512RC", ENCODING_IRC) 1028 ENCODING("i16imm", ENCODING_Iv) 1029 ENCODING("i16i8imm", ENCODING_IB) 1030 ENCODING("i32imm", ENCODING_Iv) 1031 ENCODING("i64i32imm", ENCODING_ID) 1032 ENCODING("i64i8imm", ENCODING_IB) 1033 ENCODING("i8imm", ENCODING_IB) 1034 ENCODING("u4imm", ENCODING_IB) 1035 ENCODING("u8imm", ENCODING_IB) 1036 ENCODING("i16u8imm", ENCODING_IB) 1037 ENCODING("i32u8imm", ENCODING_IB) 1038 ENCODING("i64u8imm", ENCODING_IB) 1039 // This is not a typo. Instructions like BLENDVPD put 1040 // register IDs in 8-bit immediates nowadays. 1041 ENCODING("FR32", ENCODING_IB) 1042 ENCODING("FR64", ENCODING_IB) 1043 ENCODING("FR128", ENCODING_IB) 1044 ENCODING("VR128", ENCODING_IB) 1045 ENCODING("VR256", ENCODING_IB) 1046 ENCODING("FR16X", ENCODING_IB) 1047 ENCODING("FR32X", ENCODING_IB) 1048 ENCODING("FR64X", ENCODING_IB) 1049 ENCODING("VR128X", ENCODING_IB) 1050 ENCODING("VR256X", ENCODING_IB) 1051 ENCODING("VR512", ENCODING_IB) 1052 ENCODING("TILE", ENCODING_IB) 1053 errs() << "Unhandled immediate encoding " << s << "\n"; 1054 llvm_unreachable("Unhandled immediate encoding"); 1055 } 1056 1057 OperandEncoding 1058 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1059 uint8_t OpSize) { 1060 ENCODING("RST", ENCODING_FP) 1061 ENCODING("RSTi", ENCODING_FP) 1062 ENCODING("GR16", ENCODING_RM) 1063 ENCODING("GR16orGR32orGR64",ENCODING_RM) 1064 ENCODING("GR32", ENCODING_RM) 1065 ENCODING("GR32orGR64", ENCODING_RM) 1066 ENCODING("GR64", ENCODING_RM) 1067 ENCODING("GR8", ENCODING_RM) 1068 ENCODING("VR128", ENCODING_RM) 1069 ENCODING("VR128X", ENCODING_RM) 1070 ENCODING("FR128", ENCODING_RM) 1071 ENCODING("FR64", ENCODING_RM) 1072 ENCODING("FR32", ENCODING_RM) 1073 ENCODING("FR64X", ENCODING_RM) 1074 ENCODING("FR32X", ENCODING_RM) 1075 ENCODING("FR16X", ENCODING_RM) 1076 ENCODING("VR64", ENCODING_RM) 1077 ENCODING("VR256", ENCODING_RM) 1078 ENCODING("VR256X", ENCODING_RM) 1079 ENCODING("VR512", ENCODING_RM) 1080 ENCODING("VK1", ENCODING_RM) 1081 ENCODING("VK2", ENCODING_RM) 1082 ENCODING("VK4", ENCODING_RM) 1083 ENCODING("VK8", ENCODING_RM) 1084 ENCODING("VK16", ENCODING_RM) 1085 ENCODING("VK32", ENCODING_RM) 1086 ENCODING("VK64", ENCODING_RM) 1087 ENCODING("BNDR", ENCODING_RM) 1088 ENCODING("TILE", ENCODING_RM) 1089 errs() << "Unhandled R/M register encoding " << s << "\n"; 1090 llvm_unreachable("Unhandled R/M register encoding"); 1091 } 1092 1093 OperandEncoding 1094 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1095 uint8_t OpSize) { 1096 ENCODING("GR16", ENCODING_REG) 1097 ENCODING("GR16orGR32orGR64",ENCODING_REG) 1098 ENCODING("GR32", ENCODING_REG) 1099 ENCODING("GR32orGR64", ENCODING_REG) 1100 ENCODING("GR64", ENCODING_REG) 1101 ENCODING("GR8", ENCODING_REG) 1102 ENCODING("VR128", ENCODING_REG) 1103 ENCODING("FR128", ENCODING_REG) 1104 ENCODING("FR64", ENCODING_REG) 1105 ENCODING("FR32", ENCODING_REG) 1106 ENCODING("VR64", ENCODING_REG) 1107 ENCODING("SEGMENT_REG", ENCODING_REG) 1108 ENCODING("DEBUG_REG", ENCODING_REG) 1109 ENCODING("CONTROL_REG", ENCODING_REG) 1110 ENCODING("VR256", ENCODING_REG) 1111 ENCODING("VR256X", ENCODING_REG) 1112 ENCODING("VR128X", ENCODING_REG) 1113 ENCODING("FR64X", ENCODING_REG) 1114 ENCODING("FR32X", ENCODING_REG) 1115 ENCODING("FR16X", ENCODING_REG) 1116 ENCODING("VR512", ENCODING_REG) 1117 ENCODING("VK1", ENCODING_REG) 1118 ENCODING("VK2", ENCODING_REG) 1119 ENCODING("VK4", ENCODING_REG) 1120 ENCODING("VK8", ENCODING_REG) 1121 ENCODING("VK16", ENCODING_REG) 1122 ENCODING("VK32", ENCODING_REG) 1123 ENCODING("VK64", ENCODING_REG) 1124 ENCODING("VK1Pair", ENCODING_REG) 1125 ENCODING("VK2Pair", ENCODING_REG) 1126 ENCODING("VK4Pair", ENCODING_REG) 1127 ENCODING("VK8Pair", ENCODING_REG) 1128 ENCODING("VK16Pair", ENCODING_REG) 1129 ENCODING("VK1WM", ENCODING_REG) 1130 ENCODING("VK2WM", ENCODING_REG) 1131 ENCODING("VK4WM", ENCODING_REG) 1132 ENCODING("VK8WM", ENCODING_REG) 1133 ENCODING("VK16WM", ENCODING_REG) 1134 ENCODING("VK32WM", ENCODING_REG) 1135 ENCODING("VK64WM", ENCODING_REG) 1136 ENCODING("BNDR", ENCODING_REG) 1137 ENCODING("TILE", ENCODING_REG) 1138 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1139 llvm_unreachable("Unhandled reg/opcode register encoding"); 1140 } 1141 1142 OperandEncoding 1143 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1144 uint8_t OpSize) { 1145 ENCODING("GR32", ENCODING_VVVV) 1146 ENCODING("GR64", ENCODING_VVVV) 1147 ENCODING("FR32", ENCODING_VVVV) 1148 ENCODING("FR128", ENCODING_VVVV) 1149 ENCODING("FR64", ENCODING_VVVV) 1150 ENCODING("VR128", ENCODING_VVVV) 1151 ENCODING("VR256", ENCODING_VVVV) 1152 ENCODING("FR16X", ENCODING_VVVV) 1153 ENCODING("FR32X", ENCODING_VVVV) 1154 ENCODING("FR64X", ENCODING_VVVV) 1155 ENCODING("VR128X", ENCODING_VVVV) 1156 ENCODING("VR256X", ENCODING_VVVV) 1157 ENCODING("VR512", ENCODING_VVVV) 1158 ENCODING("VK1", ENCODING_VVVV) 1159 ENCODING("VK2", ENCODING_VVVV) 1160 ENCODING("VK4", ENCODING_VVVV) 1161 ENCODING("VK8", ENCODING_VVVV) 1162 ENCODING("VK16", ENCODING_VVVV) 1163 ENCODING("VK32", ENCODING_VVVV) 1164 ENCODING("VK64", ENCODING_VVVV) 1165 ENCODING("TILE", ENCODING_VVVV) 1166 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1167 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1168 } 1169 1170 OperandEncoding 1171 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1172 uint8_t OpSize) { 1173 ENCODING("VK1WM", ENCODING_WRITEMASK) 1174 ENCODING("VK2WM", ENCODING_WRITEMASK) 1175 ENCODING("VK4WM", ENCODING_WRITEMASK) 1176 ENCODING("VK8WM", ENCODING_WRITEMASK) 1177 ENCODING("VK16WM", ENCODING_WRITEMASK) 1178 ENCODING("VK32WM", ENCODING_WRITEMASK) 1179 ENCODING("VK64WM", ENCODING_WRITEMASK) 1180 errs() << "Unhandled mask register encoding " << s << "\n"; 1181 llvm_unreachable("Unhandled mask register encoding"); 1182 } 1183 1184 OperandEncoding 1185 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1186 uint8_t OpSize) { 1187 ENCODING("i16mem", ENCODING_RM) 1188 ENCODING("i32mem", ENCODING_RM) 1189 ENCODING("i64mem", ENCODING_RM) 1190 ENCODING("i8mem", ENCODING_RM) 1191 ENCODING("shmem", ENCODING_RM) 1192 ENCODING("ssmem", ENCODING_RM) 1193 ENCODING("sdmem", ENCODING_RM) 1194 ENCODING("f128mem", ENCODING_RM) 1195 ENCODING("f256mem", ENCODING_RM) 1196 ENCODING("f512mem", ENCODING_RM) 1197 ENCODING("f64mem", ENCODING_RM) 1198 ENCODING("f32mem", ENCODING_RM) 1199 ENCODING("f16mem", ENCODING_RM) 1200 ENCODING("i128mem", ENCODING_RM) 1201 ENCODING("i256mem", ENCODING_RM) 1202 ENCODING("i512mem", ENCODING_RM) 1203 ENCODING("f80mem", ENCODING_RM) 1204 ENCODING("lea64_32mem", ENCODING_RM) 1205 ENCODING("lea64mem", ENCODING_RM) 1206 ENCODING("anymem", ENCODING_RM) 1207 ENCODING("opaquemem", ENCODING_RM) 1208 ENCODING("sibmem", ENCODING_SIB) 1209 ENCODING("vx64mem", ENCODING_VSIB) 1210 ENCODING("vx128mem", ENCODING_VSIB) 1211 ENCODING("vx256mem", ENCODING_VSIB) 1212 ENCODING("vy128mem", ENCODING_VSIB) 1213 ENCODING("vy256mem", ENCODING_VSIB) 1214 ENCODING("vx64xmem", ENCODING_VSIB) 1215 ENCODING("vx128xmem", ENCODING_VSIB) 1216 ENCODING("vx256xmem", ENCODING_VSIB) 1217 ENCODING("vy128xmem", ENCODING_VSIB) 1218 ENCODING("vy256xmem", ENCODING_VSIB) 1219 ENCODING("vy512xmem", ENCODING_VSIB) 1220 ENCODING("vz256mem", ENCODING_VSIB) 1221 ENCODING("vz512mem", ENCODING_VSIB) 1222 errs() << "Unhandled memory encoding " << s << "\n"; 1223 llvm_unreachable("Unhandled memory encoding"); 1224 } 1225 1226 OperandEncoding 1227 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1228 uint8_t OpSize) { 1229 if(OpSize != X86Local::OpSize16) { 1230 // For instructions without an OpSize prefix, a declared 16-bit register or 1231 // immediate encoding is special. 1232 ENCODING("i16imm", ENCODING_IW) 1233 } 1234 ENCODING("i16imm", ENCODING_Iv) 1235 ENCODING("i16i8imm", ENCODING_IB) 1236 ENCODING("i32imm", ENCODING_Iv) 1237 ENCODING("i32i8imm", ENCODING_IB) 1238 ENCODING("i64i32imm", ENCODING_ID) 1239 ENCODING("i64i8imm", ENCODING_IB) 1240 ENCODING("i8imm", ENCODING_IB) 1241 ENCODING("u8imm", ENCODING_IB) 1242 ENCODING("i16u8imm", ENCODING_IB) 1243 ENCODING("i32u8imm", ENCODING_IB) 1244 ENCODING("i64u8imm", ENCODING_IB) 1245 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1246 ENCODING("i16imm_brtarget", ENCODING_IW) 1247 ENCODING("i32imm_brtarget", ENCODING_ID) 1248 ENCODING("brtarget32", ENCODING_ID) 1249 ENCODING("brtarget16", ENCODING_IW) 1250 ENCODING("brtarget8", ENCODING_IB) 1251 ENCODING("i64imm", ENCODING_IO) 1252 ENCODING("offset16_8", ENCODING_Ia) 1253 ENCODING("offset16_16", ENCODING_Ia) 1254 ENCODING("offset16_32", ENCODING_Ia) 1255 ENCODING("offset32_8", ENCODING_Ia) 1256 ENCODING("offset32_16", ENCODING_Ia) 1257 ENCODING("offset32_32", ENCODING_Ia) 1258 ENCODING("offset32_64", ENCODING_Ia) 1259 ENCODING("offset64_8", ENCODING_Ia) 1260 ENCODING("offset64_16", ENCODING_Ia) 1261 ENCODING("offset64_32", ENCODING_Ia) 1262 ENCODING("offset64_64", ENCODING_Ia) 1263 ENCODING("srcidx8", ENCODING_SI) 1264 ENCODING("srcidx16", ENCODING_SI) 1265 ENCODING("srcidx32", ENCODING_SI) 1266 ENCODING("srcidx64", ENCODING_SI) 1267 ENCODING("dstidx8", ENCODING_DI) 1268 ENCODING("dstidx16", ENCODING_DI) 1269 ENCODING("dstidx32", ENCODING_DI) 1270 ENCODING("dstidx64", ENCODING_DI) 1271 errs() << "Unhandled relocation encoding " << s << "\n"; 1272 llvm_unreachable("Unhandled relocation encoding"); 1273 } 1274 1275 OperandEncoding 1276 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1277 uint8_t OpSize) { 1278 ENCODING("GR32", ENCODING_Rv) 1279 ENCODING("GR64", ENCODING_RO) 1280 ENCODING("GR16", ENCODING_Rv) 1281 ENCODING("GR8", ENCODING_RB) 1282 ENCODING("ccode", ENCODING_CC) 1283 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1284 llvm_unreachable("Unhandled opcode modifier encoding"); 1285 } 1286 #undef ENCODING 1287